Struct stm32ral::stm32l4::stm32l4r9::dfsdm1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 108 fields
pub CH0CFGR1: RWRegister<u32>,
pub CH0CFGR2: RWRegister<u32>,
pub CH0AWSCDR: RWRegister<u32>,
pub CH0WDATR: RWRegister<u32>,
pub CH0DATINR: RWRegister<u32>,
pub CH0DLYR: RWRegister<u32>,
pub CH1CFGR1: RWRegister<u32>,
pub CH1CFGR2: RWRegister<u32>,
pub CH1AWSCDR: RWRegister<u32>,
pub CH1WDATR: RWRegister<u32>,
pub CH1DATINR: RWRegister<u32>,
pub CH1DLYR: RWRegister<u32>,
pub CH2CFGR1: RWRegister<u32>,
pub CH2CFGR2: RWRegister<u32>,
pub CH2AWSCDR: RWRegister<u32>,
pub CH2WDATR: RWRegister<u32>,
pub CH2DATINR: RWRegister<u32>,
pub CH2DLYR: RWRegister<u32>,
pub CH3CFGR1: RWRegister<u32>,
pub CH3CFGR2: RWRegister<u32>,
pub CH3AWSCDR: RWRegister<u32>,
pub CH3WDATR: RWRegister<u32>,
pub CH3DATINR: RWRegister<u32>,
pub CH3DLYR: RWRegister<u32>,
pub CH4CFGR1: RWRegister<u32>,
pub CH4CFGR2: RWRegister<u32>,
pub CH4AWSCDR: RWRegister<u32>,
pub CH4WDATR: RWRegister<u32>,
pub CH4DATINR: RWRegister<u32>,
pub CH4DLYR: RWRegister<u32>,
pub CH5CFGR1: RWRegister<u32>,
pub CH5CFGR2: RWRegister<u32>,
pub CH5AWSCDR: RWRegister<u32>,
pub CH5WDATR: RWRegister<u32>,
pub CH5DATINR: RWRegister<u32>,
pub CH5DLYR: RWRegister<u32>,
pub CH6CFGR1: RWRegister<u32>,
pub CH6CFGR2: RWRegister<u32>,
pub CH6AWSCDR: RWRegister<u32>,
pub CH6WDATR: RWRegister<u32>,
pub CH6DATINR: RWRegister<u32>,
pub CH6DLYR: RWRegister<u32>,
pub CH7CFGR1: RWRegister<u32>,
pub CH7CFGR2: RWRegister<u32>,
pub CH7AWSCDR: RWRegister<u32>,
pub CH7WDATR: RWRegister<u32>,
pub CH7DATINR: RWRegister<u32>,
pub CH7DLYR: RWRegister<u32>,
pub DFSDM_FLT0CR1: RWRegister<u32>,
pub DFSDM_FLT0CR2: RWRegister<u32>,
pub DFSDM_FLT0ISR: RORegister<u32>,
pub DFSDM_FLT0ICR: RWRegister<u32>,
pub DFSDM_FLT0JCHGR: RWRegister<u32>,
pub DFSDM_FLT0FCR: RWRegister<u32>,
pub DFSDM_FLT0JDATAR: RORegister<u32>,
pub DFSDM_FLT0RDATAR: RORegister<u32>,
pub DFSDM_FLT0AWHTR: RWRegister<u32>,
pub DFSDM_FLT0AWLTR: RWRegister<u32>,
pub DFSDM_FLT0AWSR: RORegister<u32>,
pub DFSDM_FLT0AWCFR: RWRegister<u32>,
pub DFSDM_FLT0EXMAX: RORegister<u32>,
pub DFSDM_FLT0EXMIN: RORegister<u32>,
pub DFSDM_FLT0CNVTIMR: RORegister<u32>,
pub DFSDM_FLT1CR1: RWRegister<u32>,
pub DFSDM_FLT1CR2: RWRegister<u32>,
pub DFSDM_FLT1ISR: RORegister<u32>,
pub DFSDM_FLT1ICR: RWRegister<u32>,
pub DFSDM_FLT1CHGR: RWRegister<u32>,
pub DFSDM_FLT1FCR: RWRegister<u32>,
pub DFSDM_FLT1JDATAR: RORegister<u32>,
pub DFSDM_FLT1RDATAR: RORegister<u32>,
pub DFSDM_FLT1AWHTR: RWRegister<u32>,
pub DFSDM_FLT1AWLTR: RWRegister<u32>,
pub DFSDM_FLT1AWSR: RORegister<u32>,
pub DFSDM_FLT1AWCFR: RWRegister<u32>,
pub DFSDM_FLT1EXMAX: RORegister<u32>,
pub DFSDM_FLT1EXMIN: RORegister<u32>,
pub DFSDM_FLT1CNVTIMR: RORegister<u32>,
pub DFSDM_FLT2CR1: RWRegister<u32>,
pub DFSDM_FLT2CR2: RWRegister<u32>,
pub DFSDM_FLT2ISR: RORegister<u32>,
pub DFSDM_FLT2ICR: RWRegister<u32>,
pub DFSDM_FLT2JCHGR: RWRegister<u32>,
pub DFSDM_FLT2FCR: RWRegister<u32>,
pub DFSDM_FLT2JDATAR: RORegister<u32>,
pub DFSDM_FLT2RDATAR: RORegister<u32>,
pub DFSDM_FLT2AWHTR: RWRegister<u32>,
pub DFSDM_FLT2AWLTR: RWRegister<u32>,
pub DFSDM_FLT2AWSR: RORegister<u32>,
pub DFSDM_FLT2AWCFR: RWRegister<u32>,
pub DFSDM_FLT2EXMAX: RORegister<u32>,
pub DFSDM_FLT2EXMIN: RORegister<u32>,
pub DFSDM_FLT2CNVTIMR: RORegister<u32>,
pub DFSDM_FLT3CR1: RWRegister<u32>,
pub DFSDM_FLT3CR2: RWRegister<u32>,
pub DFSDM_FLT3ISR: RORegister<u32>,
pub DFSDM_FLT3ICR: RWRegister<u32>,
pub DFSDM_FLT3JCHGR: RWRegister<u32>,
pub DFSDM_FLT3FCR: RWRegister<u32>,
pub DFSDM_FLT3JDATAR: RORegister<u32>,
pub DFSDM_FLT3RDATAR: RORegister<u32>,
pub DFSDM_FLT3AWHTR: RWRegister<u32>,
pub DFSDM_FLT3AWLTR: RWRegister<u32>,
pub DFSDM_FLT3AWSR: RORegister<u32>,
pub DFSDM_FLT3AWCFR: RWRegister<u32>,
pub DFSDM_FLT3EXMAX: RORegister<u32>,
pub DFSDM_FLT3EXMIN: RORegister<u32>,
pub DFSDM_FLT3CNVTIMR: RORegister<u32>,
// some fields omitted
}
Fields
CH0CFGR1: RWRegister<u32>
channel configuration y register
CH0CFGR2: RWRegister<u32>
channel configuration y register
CH0AWSCDR: RWRegister<u32>
analog watchdog and short-circuit detector register
CH0WDATR: RWRegister<u32>
channel watchdog filter data register
CH0DATINR: RWRegister<u32>
channel data input register
CH0DLYR: RWRegister<u32>
channel y delay register
CH1CFGR1: RWRegister<u32>
CH1CFGR1
CH1CFGR2: RWRegister<u32>
CH1CFGR2
CH1AWSCDR: RWRegister<u32>
CH1AWSCDR
CH1WDATR: RWRegister<u32>
CH1WDATR
CH1DATINR: RWRegister<u32>
CH1DATINR
CH1DLYR: RWRegister<u32>
channel y delay register
CH2CFGR1: RWRegister<u32>
CH2CFGR1
CH2CFGR2: RWRegister<u32>
CH2CFGR2
CH2AWSCDR: RWRegister<u32>
CH2AWSCDR
CH2WDATR: RWRegister<u32>
CH2WDATR
CH2DATINR: RWRegister<u32>
CH2DATINR
CH2DLYR: RWRegister<u32>
channel y delay register
CH3CFGR1: RWRegister<u32>
CH3CFGR1
CH3CFGR2: RWRegister<u32>
CH3CFGR2
CH3AWSCDR: RWRegister<u32>
CH3AWSCDR
CH3WDATR: RWRegister<u32>
CH3WDATR
CH3DATINR: RWRegister<u32>
CH3DATINR
CH3DLYR: RWRegister<u32>
channel y delay register
CH4CFGR1: RWRegister<u32>
CH4CFGR1
CH4CFGR2: RWRegister<u32>
CH4CFGR2
CH4AWSCDR: RWRegister<u32>
CH4AWSCDR
CH4WDATR: RWRegister<u32>
CH4WDATR
CH4DATINR: RWRegister<u32>
CH4DATINR
CH4DLYR: RWRegister<u32>
channel y delay register
CH5CFGR1: RWRegister<u32>
CH5CFGR1
CH5CFGR2: RWRegister<u32>
CH5CFGR2
CH5AWSCDR: RWRegister<u32>
CH5AWSCDR
CH5WDATR: RWRegister<u32>
CH5WDATR
CH5DATINR: RWRegister<u32>
CH5DATINR
CH5DLYR: RWRegister<u32>
channel y delay register
CH6CFGR1: RWRegister<u32>
CH6CFGR1
CH6CFGR2: RWRegister<u32>
CH6CFGR2
CH6AWSCDR: RWRegister<u32>
CH6AWSCDR
CH6WDATR: RWRegister<u32>
CH6WDATR
CH6DATINR: RWRegister<u32>
CH6DATINR
CH6DLYR: RWRegister<u32>
channel y delay register
CH7CFGR1: RWRegister<u32>
CH7CFGR1
CH7CFGR2: RWRegister<u32>
CH7CFGR2
CH7AWSCDR: RWRegister<u32>
CH7AWSCDR
CH7WDATR: RWRegister<u32>
CH7WDATR
CH7DATINR: RWRegister<u32>
CH7DATINR
CH7DLYR: RWRegister<u32>
channel y delay register
DFSDM_FLT0CR1: RWRegister<u32>
control register 1
DFSDM_FLT0CR2: RWRegister<u32>
control register 2
DFSDM_FLT0ISR: RORegister<u32>
interrupt and status register
DFSDM_FLT0ICR: RWRegister<u32>
interrupt flag clear register
DFSDM_FLT0JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM_FLT0FCR: RWRegister<u32>
filter control register
DFSDM_FLT0JDATAR: RORegister<u32>
data register for injected group
DFSDM_FLT0RDATAR: RORegister<u32>
data register for the regular channel
DFSDM_FLT0AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM_FLT0AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM_FLT0AWSR: RORegister<u32>
analog watchdog status register
DFSDM_FLT0AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM_FLT0EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM_FLT0EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM_FLT0CNVTIMR: RORegister<u32>
conversion timer register
DFSDM_FLT1CR1: RWRegister<u32>
control register 1
DFSDM_FLT1CR2: RWRegister<u32>
control register 2
DFSDM_FLT1ISR: RORegister<u32>
interrupt and status register
DFSDM_FLT1ICR: RWRegister<u32>
interrupt flag clear register
DFSDM_FLT1CHGR: RWRegister<u32>
injected channel group selection register
DFSDM_FLT1FCR: RWRegister<u32>
filter control register
DFSDM_FLT1JDATAR: RORegister<u32>
data register for injected group
DFSDM_FLT1RDATAR: RORegister<u32>
data register for the regular channel
DFSDM_FLT1AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM_FLT1AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM_FLT1AWSR: RORegister<u32>
analog watchdog status register
DFSDM_FLT1AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM_FLT1EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM_FLT1EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM_FLT1CNVTIMR: RORegister<u32>
conversion timer register
DFSDM_FLT2CR1: RWRegister<u32>
control register 1
DFSDM_FLT2CR2: RWRegister<u32>
control register 2
DFSDM_FLT2ISR: RORegister<u32>
interrupt and status register
DFSDM_FLT2ICR: RWRegister<u32>
interrupt flag clear register
DFSDM_FLT2JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM_FLT2FCR: RWRegister<u32>
filter control register
DFSDM_FLT2JDATAR: RORegister<u32>
data register for injected group
DFSDM_FLT2RDATAR: RORegister<u32>
data register for the regular channel
DFSDM_FLT2AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM_FLT2AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM_FLT2AWSR: RORegister<u32>
analog watchdog status register
DFSDM_FLT2AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM_FLT2EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM_FLT2EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM_FLT2CNVTIMR: RORegister<u32>
conversion timer register
DFSDM_FLT3CR1: RWRegister<u32>
control register 1
DFSDM_FLT3CR2: RWRegister<u32>
control register 2
DFSDM_FLT3ISR: RORegister<u32>
interrupt and status register
DFSDM_FLT3ICR: RWRegister<u32>
interrupt flag clear register
DFSDM_FLT3JCHGR: RWRegister<u32>
injected channel group selection register
DFSDM_FLT3FCR: RWRegister<u32>
filter control register
DFSDM_FLT3JDATAR: RORegister<u32>
data register for injected group
DFSDM_FLT3RDATAR: RORegister<u32>
data register for the regular channel
DFSDM_FLT3AWHTR: RWRegister<u32>
analog watchdog high threshold register
DFSDM_FLT3AWLTR: RWRegister<u32>
analog watchdog low threshold register
DFSDM_FLT3AWSR: RORegister<u32>
analog watchdog status register
DFSDM_FLT3AWCFR: RWRegister<u32>
analog watchdog clear flag register
DFSDM_FLT3EXMAX: RORegister<u32>
Extremes detector maximum register
DFSDM_FLT3EXMIN: RORegister<u32>
Extremes detector minimum register
DFSDM_FLT3CNVTIMR: RORegister<u32>
conversion timer register