Struct stm32ral::stm32l4::peripherals::dac1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 20 fields
pub CR: RWRegister<u32>,
pub SWTRIGR: WORegister<u32>,
pub DHR12R1: RWRegister<u32>,
pub DHR12L1: RWRegister<u32>,
pub DHR8R1: RWRegister<u32>,
pub DHR12R2: RWRegister<u32>,
pub DHR12L2: RWRegister<u32>,
pub DHR8R2: RWRegister<u32>,
pub DHR12RD: RWRegister<u32>,
pub DHR12LD: RWRegister<u32>,
pub DHR8RD: RWRegister<u32>,
pub DOR1: RORegister<u32>,
pub DOR2: RORegister<u32>,
pub SR: RWRegister<u32>,
pub CCR: RWRegister<u32>,
pub MCR: RWRegister<u32>,
pub SHSR1: RWRegister<u32>,
pub SHSR2: RWRegister<u32>,
pub SHHR: RWRegister<u32>,
pub SHRR: RWRegister<u32>,
}
Fields
CR: RWRegister<u32>
control register
SWTRIGR: WORegister<u32>
software trigger register
DHR12R1: RWRegister<u32>
channel1 12-bit right-aligned data holding register
DHR12L1: RWRegister<u32>
channel1 12-bit left-aligned data holding register
DHR8R1: RWRegister<u32>
channel1 8-bit right-aligned data holding register
DHR12R2: RWRegister<u32>
channel2 12-bit right aligned data holding register
DHR12L2: RWRegister<u32>
channel2 12-bit left aligned data holding register
DHR8R2: RWRegister<u32>
channel2 8-bit right-aligned data holding register
DHR12RD: RWRegister<u32>
Dual DAC 12-bit right-aligned data holding register
DHR12LD: RWRegister<u32>
DUAL DAC 12-bit left aligned data holding register
DHR8RD: RWRegister<u32>
DUAL DAC 8-bit right aligned data holding register
DOR1: RORegister<u32>
channel1 data output register
DOR2: RORegister<u32>
channel2 data output register
SR: RWRegister<u32>
status register
CCR: RWRegister<u32>
calibration control register
MCR: RWRegister<u32>
mode control register
SHSR1: RWRegister<u32>
Sample and Hold sample time register 1
SHSR2: RWRegister<u32>
Sample and Hold sample time register 2
SHHR: RWRegister<u32>
Sample and Hold hold time register
SHRR: RWRegister<u32>
Sample and Hold refresh time register