Struct stm32ral::stm32l0::stm32l0x1::rcc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 20 fields
pub CR: RWRegister<u32>,
pub ICSCR: RWRegister<u32>,
pub CFGR: RWRegister<u32>,
pub CIER: RORegister<u32>,
pub CIFR: RORegister<u32>,
pub CICR: RORegister<u32>,
pub IOPRSTR: RWRegister<u32>,
pub AHBRSTR: RWRegister<u32>,
pub APB2RSTR: RWRegister<u32>,
pub APB1RSTR: RWRegister<u32>,
pub IOPENR: RWRegister<u32>,
pub AHBENR: RWRegister<u32>,
pub APB2ENR: RWRegister<u32>,
pub APB1ENR: RWRegister<u32>,
pub IOPSMEN: RWRegister<u32>,
pub AHBSMENR: RWRegister<u32>,
pub APB2SMENR: RWRegister<u32>,
pub APB1SMENR: RWRegister<u32>,
pub CCIPR: RWRegister<u32>,
pub CSR: RWRegister<u32>,
// some fields omitted
}
Fields
CR: RWRegister<u32>
Clock control register
ICSCR: RWRegister<u32>
Internal clock sources calibration register
CFGR: RWRegister<u32>
Clock configuration register
CIER: RORegister<u32>
Clock interrupt enable register
CIFR: RORegister<u32>
Clock interrupt flag register
CICR: RORegister<u32>
Clock interrupt clear register
IOPRSTR: RWRegister<u32>
GPIO reset register
AHBRSTR: RWRegister<u32>
AHB peripheral reset register
APB2RSTR: RWRegister<u32>
APB2 peripheral reset register
APB1RSTR: RWRegister<u32>
APB1 peripheral reset register
IOPENR: RWRegister<u32>
GPIO clock enable register
AHBENR: RWRegister<u32>
AHB peripheral clock enable register
APB2ENR: RWRegister<u32>
APB2 peripheral clock enable register
APB1ENR: RWRegister<u32>
APB1 peripheral clock enable register
IOPSMEN: RWRegister<u32>
GPIO clock enable in sleep mode register
AHBSMENR: RWRegister<u32>
AHB peripheral clock enable in sleep mode register
APB2SMENR: RWRegister<u32>
APB2 peripheral clock enable in sleep mode register
APB1SMENR: RWRegister<u32>
APB1 peripheral clock enable in sleep mode register
CCIPR: RWRegister<u32>
Clock configuration register
CSR: RWRegister<u32>
Control and status register