Struct stm32ral::stm32h7::stm32h7b3::rcc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 56 fields
pub CR: RWRegister<u32>,
pub HSICFGR: RWRegister<u32>,
pub CRRCR: RORegister<u32>,
pub CSICFGR: RWRegister<u32>,
pub CFGR: RWRegister<u32>,
pub CDCFGR1: RWRegister<u32>,
pub CDCFGR2: RWRegister<u32>,
pub SRDCFGR: RWRegister<u32>,
pub PLLCKSELR: RWRegister<u32>,
pub PLLCFGR: RWRegister<u32>,
pub PLL1DIVR: RWRegister<u32>,
pub PLL1FRACR: RWRegister<u32>,
pub PLL2DIVR: RWRegister<u32>,
pub PLL2FRACR: RWRegister<u32>,
pub PLL3DIVR: RWRegister<u32>,
pub PLL3FRACR: RWRegister<u32>,
pub CDCCIPR: RWRegister<u32>,
pub CDCCIP1R: RWRegister<u32>,
pub CDCCIP2R: RWRegister<u32>,
pub SRDCCIPR: RWRegister<u32>,
pub CIER: RWRegister<u32>,
pub CIFR: RORegister<u32>,
pub CICR: RWRegister<u32>,
pub BDCR: RWRegister<u32>,
pub CSR: RWRegister<u32>,
pub AHB3RSTR: RWRegister<u32>,
pub AHB1RSTR: RWRegister<u32>,
pub AHB2RSTR: RWRegister<u32>,
pub AHB4RSTR: RWRegister<u32>,
pub APB3RSTR: RWRegister<u32>,
pub APB1LRSTR: RWRegister<u32>,
pub APB1HRSTR: RWRegister<u32>,
pub APB2RSTR: RWRegister<u32>,
pub APB4RSTR: RWRegister<u32>,
pub GCR: RWRegister<u32>,
pub SRDAMR: RWRegister<u32>,
pub CKGAENR: RWRegister<u32>,
pub RSR: RWRegister<u32>,
pub AHB3ENR: RWRegister<u32>,
pub AHB1ENR: RWRegister<u32>,
pub AHB2ENR: RWRegister<u32>,
pub AHB4ENR: RWRegister<u32>,
pub APB3ENR: RWRegister<u32>,
pub APB1LENR: RWRegister<u32>,
pub APB1HENR: RWRegister<u32>,
pub APB2ENR: RWRegister<u32>,
pub APB4ENR: RWRegister<u32>,
pub AHB3LPENR: RWRegister<u32>,
pub AHB1LPENR: RWRegister<u32>,
pub AHB2LPENR: RWRegister<u32>,
pub AHB4LPENR: RWRegister<u32>,
pub APB3LPENR: RWRegister<u32>,
pub APB1LLPENR: RWRegister<u32>,
pub APB1HLPENR: RWRegister<u32>,
pub APB2LPENR: RWRegister<u32>,
pub APB4LPENR: RWRegister<u32>,
// some fields omitted
}
Fields
CR: RWRegister<u32>
HSICFGR: RWRegister<u32>
RCC HSI calibration register
CRRCR: RORegister<u32>
RCC clock recovery RC register
CSICFGR: RWRegister<u32>
RCC CSI calibration register
CFGR: RWRegister<u32>
CDCFGR1: RWRegister<u32>
CDCFGR2: RWRegister<u32>
SRDCFGR: RWRegister<u32>
PLLCKSELR: RWRegister<u32>
PLLCFGR: RWRegister<u32>
PLL1DIVR: RWRegister<u32>
PLL1FRACR: RWRegister<u32>
PLL2DIVR: RWRegister<u32>
PLL2FRACR: RWRegister<u32>
PLL3DIVR: RWRegister<u32>
PLL3FRACR: RWRegister<u32>
CDCCIPR: RWRegister<u32>
RCC CPU domain kernel clock configuration register
CDCCIP1R: RWRegister<u32>
RCC CPU domain kernel clock configuration register
CDCCIP2R: RWRegister<u32>
RCC CPU domain kernel clock configuration register
SRDCCIPR: RWRegister<u32>
RCC SmartRun domain kernel clock configuration register
CIER: RWRegister<u32>
CIFR: RORegister<u32>
CICR: RWRegister<u32>
BDCR: RWRegister<u32>
RCC Backup domain control register
CSR: RWRegister<u32>
RCC clock control and status register
AHB3RSTR: RWRegister<u32>
AHB1RSTR: RWRegister<u32>
AHB2RSTR: RWRegister<u32>
AHB4RSTR: RWRegister<u32>
APB3RSTR: RWRegister<u32>
APB1LRSTR: RWRegister<u32>
APB1HRSTR: RWRegister<u32>
APB2RSTR: RWRegister<u32>
APB4RSTR: RWRegister<u32>
GCR: RWRegister<u32>
Global Control Register
SRDAMR: RWRegister<u32>
RCC SmartRun domain Autonomous mode register
CKGAENR: RWRegister<u32>
RCC AXI clocks gating enable register
RSR: RWRegister<u32>
RCC reset status register
AHB3ENR: RWRegister<u32>
AHB1ENR: RWRegister<u32>
AHB2ENR: RWRegister<u32>
AHB4ENR: RWRegister<u32>
APB3ENR: RWRegister<u32>
APB1LENR: RWRegister<u32>
APB1HENR: RWRegister<u32>
APB2ENR: RWRegister<u32>
APB4ENR: RWRegister<u32>
AHB3LPENR: RWRegister<u32>
AHB1LPENR: RWRegister<u32>
AHB2LPENR: RWRegister<u32>
AHB4LPENR: RWRegister<u32>
APB3LPENR: RWRegister<u32>
APB1LLPENR: RWRegister<u32>
APB1HLPENR: RWRegister<u32>
APB2LPENR: RWRegister<u32>
APB4LPENR: RWRegister<u32>