Struct stm32ral::stm32h7::peripherals::rcc_v1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 73 fields
pub CR: RWRegister<u32>,
pub ICSCR: RWRegister<u32>,
pub CRRCR: RORegister<u32>,
pub CFGR: RWRegister<u32>,
pub D1CFGR: RWRegister<u32>,
pub D2CFGR: RWRegister<u32>,
pub D3CFGR: RWRegister<u32>,
pub PLLCKSELR: RWRegister<u32>,
pub PLLCFGR: RWRegister<u32>,
pub PLL1DIVR: RWRegister<u32>,
pub PLL1FRACR: RWRegister<u32>,
pub PLL2DIVR: RWRegister<u32>,
pub PLL2FRACR: RWRegister<u32>,
pub PLL3DIVR: RWRegister<u32>,
pub PLL3FRACR: RWRegister<u32>,
pub D1CCIPR: RWRegister<u32>,
pub D2CCIP1R: RWRegister<u32>,
pub D2CCIP2R: RWRegister<u32>,
pub D3CCIPR: RWRegister<u32>,
pub CIER: RWRegister<u32>,
pub CIFR: RORegister<u32>,
pub CICR: RWRegister<u32>,
pub BDCR: RWRegister<u32>,
pub CSR: RWRegister<u32>,
pub AHB3RSTR: RWRegister<u32>,
pub AHB1RSTR: RWRegister<u32>,
pub AHB2RSTR: RWRegister<u32>,
pub AHB4RSTR: RWRegister<u32>,
pub APB3RSTR: RWRegister<u32>,
pub APB1LRSTR: RWRegister<u32>,
pub APB1HRSTR: RWRegister<u32>,
pub APB2RSTR: RWRegister<u32>,
pub APB4RSTR: RWRegister<u32>,
pub GCR: RWRegister<u32>,
pub D3AMR: RWRegister<u32>,
pub RSR: RWRegister<u32>,
pub AHB3ENR: RWRegister<u32>,
pub AHB1ENR: RWRegister<u32>,
pub AHB2ENR: RWRegister<u32>,
pub AHB4ENR: RWRegister<u32>,
pub APB3ENR: RWRegister<u32>,
pub APB1LENR: RWRegister<u32>,
pub APB1HENR: RWRegister<u32>,
pub APB2ENR: RWRegister<u32>,
pub APB4ENR: RWRegister<u32>,
pub AHB3LPENR: RWRegister<u32>,
pub AHB1LPENR: RWRegister<u32>,
pub AHB2LPENR: RWRegister<u32>,
pub AHB4LPENR: RWRegister<u32>,
pub APB3LPENR: RWRegister<u32>,
pub APB1LLPENR: RWRegister<u32>,
pub APB1HLPENR: RWRegister<u32>,
pub APB2LPENR: RWRegister<u32>,
pub APB4LPENR: RWRegister<u32>,
pub C1_RSR: RWRegister<u32>,
pub C1_AHB3ENR: RWRegister<u32>,
pub C1_AHB1ENR: RWRegister<u32>,
pub C1_AHB2ENR: RWRegister<u32>,
pub C1_AHB4ENR: RWRegister<u32>,
pub C1_APB3ENR: RWRegister<u32>,
pub C1_APB1LENR: RWRegister<u32>,
pub C1_APB1HENR: RWRegister<u32>,
pub C1_APB2ENR: RWRegister<u32>,
pub C1_APB4ENR: RWRegister<u32>,
pub C1_AHB3LPENR: RWRegister<u32>,
pub C1_AHB1LPENR: RWRegister<u32>,
pub C1_AHB2LPENR: RWRegister<u32>,
pub C1_AHB4LPENR: RWRegister<u32>,
pub C1_APB3LPENR: RWRegister<u32>,
pub C1_APB1LLPENR: RWRegister<u32>,
pub C1_APB1HLPENR: RWRegister<u32>,
pub C1_APB2LPENR: RWRegister<u32>,
pub C1_APB4LPENR: RWRegister<u32>,
// some fields omitted
}
Fields
CR: RWRegister<u32>
clock control register
ICSCR: RWRegister<u32>
RCC Internal Clock Source Calibration Register
CRRCR: RORegister<u32>
RCC Clock Recovery RC Register
CFGR: RWRegister<u32>
RCC Clock Configuration Register
D1CFGR: RWRegister<u32>
RCC Domain 1 Clock Configuration Register
D2CFGR: RWRegister<u32>
RCC Domain 2 Clock Configuration Register
D3CFGR: RWRegister<u32>
RCC Domain 3 Clock Configuration Register
PLLCKSELR: RWRegister<u32>
RCC PLLs Clock Source Selection Register
PLLCFGR: RWRegister<u32>
RCC PLLs Configuration Register
PLL1DIVR: RWRegister<u32>
RCC PLL1 Dividers Configuration Register
PLL1FRACR: RWRegister<u32>
RCC PLL1 Fractional Divider Register
PLL2DIVR: RWRegister<u32>
RCC PLL2 Dividers Configuration Register
PLL2FRACR: RWRegister<u32>
RCC PLL2 Fractional Divider Register
PLL3DIVR: RWRegister<u32>
RCC PLL3 Dividers Configuration Register
PLL3FRACR: RWRegister<u32>
RCC PLL3 Fractional Divider Register
D1CCIPR: RWRegister<u32>
RCC Domain 1 Kernel Clock Configuration Register
D2CCIP1R: RWRegister<u32>
RCC Domain 2 Kernel Clock Configuration Register
D2CCIP2R: RWRegister<u32>
RCC Domain 2 Kernel Clock Configuration Register
D3CCIPR: RWRegister<u32>
RCC Domain 3 Kernel Clock Configuration Register
CIER: RWRegister<u32>
RCC Clock Source Interrupt Enable Register
CIFR: RORegister<u32>
RCC Clock Source Interrupt Flag Register
CICR: RWRegister<u32>
RCC Clock Source Interrupt Clear Register
BDCR: RWRegister<u32>
RCC Backup Domain Control Register
CSR: RWRegister<u32>
RCC Clock Control and Status Register
AHB3RSTR: RWRegister<u32>
RCC AHB3 Reset Register
AHB1RSTR: RWRegister<u32>
RCC AHB1 Peripheral Reset Register
AHB2RSTR: RWRegister<u32>
RCC AHB2 Peripheral Reset Register
AHB4RSTR: RWRegister<u32>
RCC AHB4 Peripheral Reset Register
APB3RSTR: RWRegister<u32>
RCC APB3 Peripheral Reset Register
APB1LRSTR: RWRegister<u32>
RCC APB1 Peripheral Reset Register
APB1HRSTR: RWRegister<u32>
RCC APB1 Peripheral Reset Register
APB2RSTR: RWRegister<u32>
RCC APB2 Peripheral Reset Register
APB4RSTR: RWRegister<u32>
RCC APB4 Peripheral Reset Register
GCR: RWRegister<u32>
RCC Global Control Register
D3AMR: RWRegister<u32>
RCC D3 Autonomous mode Register
RSR: RWRegister<u32>
RCC Reset Status Register
AHB3ENR: RWRegister<u32>
RCC AHB3 Clock Register
AHB1ENR: RWRegister<u32>
RCC AHB1 Clock Register
AHB2ENR: RWRegister<u32>
RCC AHB2 Clock Register
AHB4ENR: RWRegister<u32>
RCC AHB4 Clock Register
APB3ENR: RWRegister<u32>
RCC APB3 Clock Register
APB1LENR: RWRegister<u32>
RCC APB1 Clock Register
APB1HENR: RWRegister<u32>
RCC APB1 Clock Register
APB2ENR: RWRegister<u32>
RCC APB2 Clock Register
APB4ENR: RWRegister<u32>
RCC APB4 Clock Register
AHB3LPENR: RWRegister<u32>
RCC AHB3 Sleep Clock Register
AHB1LPENR: RWRegister<u32>
RCC AHB1 Sleep Clock Register
AHB2LPENR: RWRegister<u32>
RCC AHB2 Sleep Clock Register
AHB4LPENR: RWRegister<u32>
RCC AHB4 Sleep Clock Register
APB3LPENR: RWRegister<u32>
RCC APB3 Sleep Clock Register
APB1LLPENR: RWRegister<u32>
RCC APB1 Low Sleep Clock Register
APB1HLPENR: RWRegister<u32>
RCC APB1 High Sleep Clock Register
APB2LPENR: RWRegister<u32>
RCC APB2 Sleep Clock Register
APB4LPENR: RWRegister<u32>
RCC APB4 Sleep Clock Register
C1_RSR: RWRegister<u32>
RCC Reset Status Register
C1_AHB3ENR: RWRegister<u32>
RCC AHB3 Clock Register
C1_AHB1ENR: RWRegister<u32>
RCC AHB1 Clock Register
C1_AHB2ENR: RWRegister<u32>
RCC AHB2 Clock Register
C1_AHB4ENR: RWRegister<u32>
RCC AHB4 Clock Register
C1_APB3ENR: RWRegister<u32>
RCC APB3 Clock Register
C1_APB1LENR: RWRegister<u32>
RCC APB1 Clock Register
C1_APB1HENR: RWRegister<u32>
RCC APB1 Clock Register
C1_APB2ENR: RWRegister<u32>
RCC APB2 Clock Register
C1_APB4ENR: RWRegister<u32>
RCC APB4 Clock Register
C1_AHB3LPENR: RWRegister<u32>
RCC AHB3 Sleep Clock Register
C1_AHB1LPENR: RWRegister<u32>
RCC AHB1 Sleep Clock Register
C1_AHB2LPENR: RWRegister<u32>
RCC AHB2 Sleep Clock Register
C1_AHB4LPENR: RWRegister<u32>
RCC AHB4 Sleep Clock Register
C1_APB3LPENR: RWRegister<u32>
RCC APB3 Sleep Clock Register
C1_APB1LLPENR: RWRegister<u32>
RCC APB1 Low Sleep Clock Register
C1_APB1HLPENR: RWRegister<u32>
RCC APB1 High Sleep Clock Register
C1_APB2LPENR: RWRegister<u32>
RCC APB2 Sleep Clock Register
C1_APB4LPENR: RWRegister<u32>
RCC APB4 Sleep Clock Register