Struct stm32ral::stm32h7::peripherals::hrtim_common_v2::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 25 fields
pub CR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub ISR: RWRegister<u32>,
pub ICR: RWRegister<u32>,
pub IER: RWRegister<u32>,
pub OENR: WORegister<u32>,
pub DISR: RWRegister<u32>,
pub ODSR: RORegister<u32>,
pub BMCR: RWRegister<u32>,
pub BMTRG: RWRegister<u32>,
pub BMCMPR6: RWRegister<u32>,
pub BMPER: RWRegister<u32>,
pub EECR1: RWRegister<u32>,
pub EECR2: RWRegister<u32>,
pub EECR3: RWRegister<u32>,
pub ADC1R: RWRegister<u32>,
pub ADC2R: RWRegister<u32>,
pub ADC3R: RWRegister<u32>,
pub ADC4R: RWRegister<u32>,
pub DLLCR: RWRegister<u32>,
pub FLTINR1: RWRegister<u32>,
pub FLTINR2: RWRegister<u32>,
pub BDMUPDR: RWRegister<u32>,
pub BDTxUPR: RWRegister<u32>,
pub BDMADR: RWRegister<u32>,
// some fields omitted
}
Fields
CR1: RWRegister<u32>
Control Register 1
CR2: RWRegister<u32>
Control Register 2
ISR: RWRegister<u32>
Interrupt Status Register
ICR: RWRegister<u32>
Interrupt Clear Register
IER: RWRegister<u32>
Interrupt Enable Register
OENR: WORegister<u32>
Output Enable Register
DISR: RWRegister<u32>
DISR
ODSR: RORegister<u32>
Output Disable Status Register
BMCR: RWRegister<u32>
Burst Mode Control Register
BMTRG: RWRegister<u32>
BMTRG
BMCMPR6: RWRegister<u32>
BMCMPR6
BMPER: RWRegister<u32>
Burst Mode Period Register
EECR1: RWRegister<u32>
Timer External Event Control Register 1
EECR2: RWRegister<u32>
Timer External Event Control Register 2
EECR3: RWRegister<u32>
Timer External Event Control Register 3
ADC1R: RWRegister<u32>
ADC Trigger 1 Register
ADC2R: RWRegister<u32>
ADC Trigger 2 Register
ADC3R: RWRegister<u32>
ADC Trigger 3 Register
ADC4R: RWRegister<u32>
ADC Trigger 4 Register
DLLCR: RWRegister<u32>
DLL Control Register
FLTINR1: RWRegister<u32>
HRTIM Fault Input Register 1
FLTINR2: RWRegister<u32>
HRTIM Fault Input Register 2
BDMUPDR: RWRegister<u32>
BDMUPDR
BDTxUPR: RWRegister<u32>
Burst DMA Timerx update Register
BDMADR: RWRegister<u32>
Burst DMA Data register