Struct stm32ral::stm32h7::peripherals::ethernet_mac_v2::ResetValues[−][src]

pub struct ResetValues {Show 90 fields
    pub MACCR: u32,
    pub MACECR: u32,
    pub MACPFR: u32,
    pub MACWTR: u32,
    pub MACHT0R: u32,
    pub MACHT1R: u32,
    pub MACVTR: u32,
    pub MACVHTR: u32,
    pub MACVIR: u32,
    pub MACIVIR: u32,
    pub MACQTxFCR: u32,
    pub MACRxFCR: u32,
    pub MACISR: u32,
    pub MACIER: u32,
    pub MACRxTxSR: u32,
    pub MACPCSR: u32,
    pub MACRWKPFR: u32,
    pub MACLCSR: u32,
    pub MACLTCR: u32,
    pub MACLETR: u32,
    pub MAC1USTCR: u32,
    pub MACVR: u32,
    pub MACDR: u32,
    pub MACHWF1R: u32,
    pub MACHWF2R: u32,
    pub MACMDIOAR: u32,
    pub MACMDIODR: u32,
    pub MACA0HR: u32,
    pub MACA0LR: u32,
    pub MACA1HR: u32,
    pub MACA1LR: u32,
    pub MACA2HR: u32,
    pub MACA2LR: u32,
    pub MACA3HR: u32,
    pub MACA3LR: u32,
    pub MMC_CONTROL: u32,
    pub MMC_RX_INTERRUPT: u32,
    pub MMC_TX_INTERRUPT: u32,
    pub MMC_RX_INTERRUPT_MASK: u32,
    pub MMC_TX_INTERRUPT_MASK: u32,
    pub TX_SINGLE_COLLISION_GOOD_PACKETS: u32,
    pub TX_MULTIPLE_COLLISION_GOOD_PACKETS: u32,
    pub TX_PACKET_COUNT_GOOD: u32,
    pub RX_CRC_ERROR_PACKETS: u32,
    pub RX_ALIGNMENT_ERROR_PACKETS: u32,
    pub RX_UNICAST_PACKETS_GOOD: u32,
    pub TX_LPI_USEC_CNTR: u32,
    pub TX_LPI_TRAN_CNTR: u32,
    pub RX_LPI_USEC_CNTR: u32,
    pub RX_LPI_TRAN_CNTR: u32,
    pub MACL3L4C0R: u32,
    pub MACL4A0R: u32,
    pub MACL3A00R: u32,
    pub MACL3A10R: u32,
    pub MACL3A20: u32,
    pub MACL3A30: u32,
    pub MACL3L4C1R: u32,
    pub MACL4A1R: u32,
    pub MACL3A01R: u32,
    pub MACL3A11R: u32,
    pub MACL3A21R: u32,
    pub MACL3A31R: u32,
    pub MACARPAR: u32,
    pub MACTSCR: u32,
    pub MACSSIR: u32,
    pub MACSTSR: u32,
    pub MACSTNR: u32,
    pub MACSTSUR: u32,
    pub MACSTNUR: u32,
    pub MACTSAR: u32,
    pub MACTSSR: u32,
    pub MACTxTSSNR: u32,
    pub MACTxTSSSR: u32,
    pub MACACR: u32,
    pub MACATSNR: u32,
    pub MACATSSR: u32,
    pub MACTSIACR: u32,
    pub MACTSEACR: u32,
    pub MACTSICNR: u32,
    pub MACTSECNR: u32,
    pub MACPPSCR: u32,
    pub MACPPSTTSR: u32,
    pub MACPPSTTNR: u32,
    pub MACPPSIR: u32,
    pub MACPPSWR: u32,
    pub MACPOCR: u32,
    pub MACSPI0R: u32,
    pub MACSPI1R: u32,
    pub MACSPI2R: u32,
    pub MACLMIR: u32,
}

Fields

MACCR: u32MACECR: u32MACPFR: u32MACWTR: u32MACHT0R: u32MACHT1R: u32MACVTR: u32MACVHTR: u32MACVIR: u32MACIVIR: u32MACQTxFCR: u32MACRxFCR: u32MACISR: u32MACIER: u32MACRxTxSR: u32MACPCSR: u32MACRWKPFR: u32MACLCSR: u32MACLTCR: u32MACLETR: u32MAC1USTCR: u32MACVR: u32MACDR: u32MACHWF1R: u32MACHWF2R: u32MACMDIOAR: u32MACMDIODR: u32MACA0HR: u32MACA0LR: u32MACA1HR: u32MACA1LR: u32MACA2HR: u32MACA2LR: u32MACA3HR: u32MACA3LR: u32MMC_CONTROL: u32MMC_RX_INTERRUPT: u32MMC_TX_INTERRUPT: u32MMC_RX_INTERRUPT_MASK: u32MMC_TX_INTERRUPT_MASK: u32TX_SINGLE_COLLISION_GOOD_PACKETS: u32TX_MULTIPLE_COLLISION_GOOD_PACKETS: u32TX_PACKET_COUNT_GOOD: u32RX_CRC_ERROR_PACKETS: u32RX_ALIGNMENT_ERROR_PACKETS: u32RX_UNICAST_PACKETS_GOOD: u32TX_LPI_USEC_CNTR: u32TX_LPI_TRAN_CNTR: u32RX_LPI_USEC_CNTR: u32RX_LPI_TRAN_CNTR: u32MACL3L4C0R: u32MACL4A0R: u32MACL3A00R: u32MACL3A10R: u32MACL3A20: u32MACL3A30: u32MACL3L4C1R: u32MACL4A1R: u32MACL3A01R: u32MACL3A11R: u32MACL3A21R: u32MACL3A31R: u32MACARPAR: u32MACTSCR: u32MACSSIR: u32MACSTSR: u32MACSTNR: u32MACSTSUR: u32MACSTNUR: u32MACTSAR: u32MACTSSR: u32MACTxTSSNR: u32MACTxTSSSR: u32MACACR: u32MACATSNR: u32MACATSSR: u32MACTSIACR: u32MACTSEACR: u32MACTSICNR: u32MACTSECNR: u32MACPPSCR: u32MACPPSTTSR: u32MACPPSTTNR: u32MACPPSIR: u32MACPPSWR: u32MACPOCR: u32MACSPI0R: u32MACSPI1R: u32MACSPI2R: u32MACLMIR: u32