Struct stm32ral::stm32g0::peripherals::tim1_v2::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 27 fields
pub CR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub SMCR: RWRegister<u32>,
pub DIER: RWRegister<u32>,
pub SR: RWRegister<u32>,
pub EGR: WORegister<u32>,
pub CCMR1: RWRegister<u32>,
pub CCMR2: RWRegister<u32>,
pub CCER: RWRegister<u32>,
pub CNT: RWRegister<u32>,
pub PSC: RWRegister<u32>,
pub ARR: RWRegister<u32>,
pub RCR: RWRegister<u32>,
pub CCR1: RWRegister<u32>,
pub CCR2: RWRegister<u32>,
pub CCR3: RWRegister<u32>,
pub CCR4: RWRegister<u32>,
pub BDTR: RWRegister<u32>,
pub DCR: RWRegister<u32>,
pub DMAR: RWRegister<u32>,
pub OR1: RWRegister<u32>,
pub CCMR3_Output: RWRegister<u32>,
pub CCR5: RWRegister<u32>,
pub CCR6: RWRegister<u32>,
pub AF1: RWRegister<u32>,
pub AF2: RWRegister<u32>,
pub TISEL: RWRegister<u32>,
}
Fields
CR1: RWRegister<u32>
control register 1
CR2: RWRegister<u32>
control register 2
SMCR: RWRegister<u32>
slave mode control register
DIER: RWRegister<u32>
DMA/Interrupt enable register
SR: RWRegister<u32>
status register
EGR: WORegister<u32>
event generation register
CCMR1: RWRegister<u32>
CCMR1_Output and CCMR1_Input CCMR1_Output: capture/compare mode register 1 (output mode) CCMR1_Input: capture/compare mode register 1 (output mode)
CCMR2: RWRegister<u32>
CCMR2_Output and CCMR2_Input CCMR2_Output: capture/compare mode register 2 (output mode) CCMR2_Input: capture/compare mode register 2 (output mode)
CCER: RWRegister<u32>
capture/compare enable register
CNT: RWRegister<u32>
counter
PSC: RWRegister<u32>
prescaler
ARR: RWRegister<u32>
auto-reload register
RCR: RWRegister<u32>
repetition counter register
CCR1: RWRegister<u32>
capture/compare register 1
CCR2: RWRegister<u32>
capture/compare register 2
CCR3: RWRegister<u32>
capture/compare register 3
CCR4: RWRegister<u32>
capture/compare register 4
BDTR: RWRegister<u32>
break and dead-time register
DCR: RWRegister<u32>
DMA control register
DMAR: RWRegister<u32>
DMA address for full transfer
OR1: RWRegister<u32>
option register 1
CCMR3_Output: RWRegister<u32>
capture/compare mode register 2 (output mode)
CCR5: RWRegister<u32>
capture/compare register 4
CCR6: RWRegister<u32>
capture/compare register 4
AF1: RWRegister<u32>
DMA address for full transfer
AF2: RWRegister<u32>
DMA address for full transfer
TISEL: RWRegister<u32>
TIM1 timer input selection register