Struct stm32ral::stm32g0::peripherals::dma1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 30 fields
pub ISR: RORegister<u32>,
pub IFCR: RORegister<u32>,
pub CR1: RWRegister<u32>,
pub NDTR1: RWRegister<u32>,
pub PAR1: RWRegister<u32>,
pub MAR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub NDTR2: RWRegister<u32>,
pub PAR2: RWRegister<u32>,
pub MAR2: RWRegister<u32>,
pub CR3: RWRegister<u32>,
pub NDTR3: RWRegister<u32>,
pub PAR3: RWRegister<u32>,
pub MAR3: RWRegister<u32>,
pub CR4: RWRegister<u32>,
pub NDTR4: RWRegister<u32>,
pub PAR4: RWRegister<u32>,
pub MAR4: RWRegister<u32>,
pub CR5: RWRegister<u32>,
pub NDTR5: RWRegister<u32>,
pub PAR5: RWRegister<u32>,
pub MAR5: RWRegister<u32>,
pub CR6: RWRegister<u32>,
pub NDTR6: RWRegister<u32>,
pub PAR6: RWRegister<u32>,
pub MAR6: RWRegister<u32>,
pub CR7: RWRegister<u32>,
pub NDTR7: RWRegister<u32>,
pub PAR7: RWRegister<u32>,
pub MAR7: RWRegister<u32>,
// some fields omitted
}
Fields
ISR: RORegister<u32>
low interrupt status register
IFCR: RORegister<u32>
high interrupt status register
CR1: RWRegister<u32>
DMA channel 1 configuration register
NDTR1: RWRegister<u32>
DMA channel 1 number of data tegister
PAR1: RWRegister<u32>
DMA channel 1 peripheral address
MAR1: RWRegister<u32>
DMA channel 1 memory address
CR2: RWRegister<u32>
DMA channel 1 configuration register
NDTR2: RWRegister<u32>
DMA channel 1 number of data tegister
PAR2: RWRegister<u32>
DMA channel 1 peripheral address
MAR2: RWRegister<u32>
DMA channel 1 memory address
CR3: RWRegister<u32>
DMA channel 1 configuration register
NDTR3: RWRegister<u32>
DMA channel 1 number of data tegister
PAR3: RWRegister<u32>
DMA channel 1 peripheral address
MAR3: RWRegister<u32>
DMA channel 1 memory address
CR4: RWRegister<u32>
DMA channel 1 configuration register
NDTR4: RWRegister<u32>
DMA channel 1 number of data tegister
PAR4: RWRegister<u32>
DMA channel 1 peripheral address
MAR4: RWRegister<u32>
DMA channel 1 memory address
CR5: RWRegister<u32>
DMA channel 1 configuration register
NDTR5: RWRegister<u32>
DMA channel 1 number of data tegister
PAR5: RWRegister<u32>
DMA channel 1 peripheral address
MAR5: RWRegister<u32>
DMA channel 1 memory address
CR6: RWRegister<u32>
DMA channel 1 configuration register
NDTR6: RWRegister<u32>
DMA channel 1 number of data tegister
PAR6: RWRegister<u32>
DMA channel 1 peripheral address
MAR6: RWRegister<u32>
DMA channel 1 memory address
CR7: RWRegister<u32>
DMA channel 1 configuration register
NDTR7: RWRegister<u32>
DMA channel 1 number of data tegister
PAR7: RWRegister<u32>
DMA channel 1 peripheral address
MAR7: RWRegister<u32>
DMA channel 1 memory address