Struct stm32ral::stm32f7::peripherals::otg_hs_device_v1::ResetValues [−][src]
pub struct ResetValues {Show 101 fields
pub OTG_HS_DCFG: u32,
pub OTG_HS_DCTL: u32,
pub OTG_HS_DSTS: u32,
pub OTG_HS_DIEPMSK: u32,
pub OTG_HS_DOEPMSK: u32,
pub OTG_HS_DAINT: u32,
pub OTG_HS_DAINTMSK: u32,
pub OTG_HS_DVBUSDIS: u32,
pub OTG_HS_DVBUSPULSE: u32,
pub OTG_HS_DTHRCTL: u32,
pub OTG_HS_DIEPEMPMSK: u32,
pub OTG_HS_DEACHINT: u32,
pub OTG_HS_DEACHINTMSK: u32,
pub OTG_HS_DIEPCTL0: u32,
pub OTG_HS_DIEPINT0: u32,
pub OTG_HS_DIEPTSIZ0: u32,
pub OTG_HS_DIEPDMA0: u32,
pub OTG_HS_DTXFSTS0: u32,
pub OTG_HS_DIEPCTL1: u32,
pub OTG_HS_DIEPINT1: u32,
pub OTG_HS_DIEPTSIZ1: u32,
pub OTG_HS_DIEPDMA1: u32,
pub OTG_HS_DTXFSTS1: u32,
pub OTG_HS_DIEPCTL2: u32,
pub OTG_HS_DIEPINT2: u32,
pub OTG_HS_DIEPTSIZ2: u32,
pub OTG_HS_DIEPDMA2: u32,
pub OTG_HS_DTXFSTS2: u32,
pub OTG_HS_DIEPCTL3: u32,
pub OTG_HS_DIEPINT3: u32,
pub OTG_HS_DIEPTSIZ3: u32,
pub OTG_HS_DIEPDMA3: u32,
pub OTG_HS_DTXFSTS3: u32,
pub OTG_HS_DIEPCTL4: u32,
pub OTG_HS_DIEPINT4: u32,
pub OTG_HS_DIEPTSIZ4: u32,
pub OTG_HS_DIEPDMA4: u32,
pub OTG_HS_DTXFSTS4: u32,
pub OTG_HS_DIEPCTL5: u32,
pub OTG_HS_DIEPINT5: u32,
pub OTG_HS_DIEPTSIZ5: u32,
pub OTG_HS_DIEPDMA5: u32,
pub OTG_HS_DTXFSTS5: u32,
pub OTG_HS_DIEPCTL6: u32,
pub OTG_HS_DIEPINT6: u32,
pub OTG_HS_DIEPTSIZ6: u32,
pub OTG_HS_DIEPDMA6: u32,
pub OTG_HS_DTXFSTS6: u32,
pub OTG_HS_DIEPCTL7: u32,
pub OTG_HS_DIEPINT7: u32,
pub OTG_HS_DIEPTSIZ7: u32,
pub OTG_HS_DIEPDMA7: u32,
pub OTG_HS_DTXFSTS7: u32,
pub OTG_HS_DIEPDMA8: u32,
pub OTG_HS_DIEPDMA9: u32,
pub OTG_HS_DIEPDMA10: u32,
pub OTG_HS_DIEPDMA11: u32,
pub OTG_HS_DIEPDMA12: u32,
pub OTG_HS_DIEPDMA13: u32,
pub OTG_HS_DIEPDMA14: u32,
pub OTG_HS_DIEPDMA15: u32,
pub OTG_HS_DOEPCTL0: u32,
pub OTG_HS_DOEPINT0: u32,
pub OTG_HS_DOEPTSIZ0: u32,
pub OTG_HS_DOEPDMA0: u32,
pub OTG_HS_DOEPCTL1: u32,
pub OTG_HS_DOEPINT1: u32,
pub OTG_HS_DOEPTSIZ1: u32,
pub OTG_HS_DOEPDMA1: u32,
pub OTG_HS_DOEPCTL2: u32,
pub OTG_HS_DOEPINT2: u32,
pub OTG_HS_DOEPTSIZ2: u32,
pub OTG_HS_DOEPDMA2: u32,
pub OTG_HS_DOEPCTL3: u32,
pub OTG_HS_DOEPINT3: u32,
pub OTG_HS_DOEPTSIZ3: u32,
pub OTG_HS_DOEPDMA3: u32,
pub OTG_HS_DOEPCTL4: u32,
pub OTG_HS_DOEPINT4: u32,
pub OTG_HS_DOEPTSIZ4: u32,
pub OTG_HS_DOEPDMA4: u32,
pub OTG_HS_DOEPCTL5: u32,
pub OTG_HS_DOEPINT5: u32,
pub OTG_HS_DOEPTSIZ5: u32,
pub OTG_HS_DOEPDMA5: u32,
pub OTG_HS_DOEPCTL6: u32,
pub OTG_HS_DOEPINT6: u32,
pub OTG_HS_DOEPTSIZ6: u32,
pub OTG_HS_DOEPDMA6: u32,
pub OTG_HS_DOEPCTL7: u32,
pub OTG_HS_DOEPINT7: u32,
pub OTG_HS_DOEPTSIZ7: u32,
pub OTG_HS_DOEPDMA7: u32,
pub OTG_HS_DOEPDMA8: u32,
pub OTG_HS_DOEPDMA9: u32,
pub OTG_HS_DOEPDMA10: u32,
pub OTG_HS_DOEPDMA11: u32,
pub OTG_HS_DOEPDMA12: u32,
pub OTG_HS_DOEPDMA13: u32,
pub OTG_HS_DOEPDMA14: u32,
pub OTG_HS_DOEPDMA15: u32,
}Fields
OTG_HS_DCFG: u32OTG_HS_DCTL: u32OTG_HS_DSTS: u32OTG_HS_DIEPMSK: u32OTG_HS_DOEPMSK: u32OTG_HS_DAINT: u32OTG_HS_DAINTMSK: u32OTG_HS_DVBUSDIS: u32OTG_HS_DVBUSPULSE: u32OTG_HS_DTHRCTL: u32OTG_HS_DIEPEMPMSK: u32OTG_HS_DEACHINT: u32OTG_HS_DEACHINTMSK: u32OTG_HS_DIEPCTL0: u32OTG_HS_DIEPINT0: u32OTG_HS_DIEPTSIZ0: u32OTG_HS_DIEPDMA0: u32OTG_HS_DTXFSTS0: u32OTG_HS_DIEPCTL1: u32OTG_HS_DIEPINT1: u32OTG_HS_DIEPTSIZ1: u32OTG_HS_DIEPDMA1: u32OTG_HS_DTXFSTS1: u32OTG_HS_DIEPCTL2: u32OTG_HS_DIEPINT2: u32OTG_HS_DIEPTSIZ2: u32OTG_HS_DIEPDMA2: u32OTG_HS_DTXFSTS2: u32OTG_HS_DIEPCTL3: u32OTG_HS_DIEPINT3: u32OTG_HS_DIEPTSIZ3: u32OTG_HS_DIEPDMA3: u32OTG_HS_DTXFSTS3: u32OTG_HS_DIEPCTL4: u32OTG_HS_DIEPINT4: u32OTG_HS_DIEPTSIZ4: u32OTG_HS_DIEPDMA4: u32OTG_HS_DTXFSTS4: u32OTG_HS_DIEPCTL5: u32OTG_HS_DIEPINT5: u32OTG_HS_DIEPTSIZ5: u32OTG_HS_DIEPDMA5: u32OTG_HS_DTXFSTS5: u32OTG_HS_DIEPCTL6: u32OTG_HS_DIEPINT6: u32OTG_HS_DIEPTSIZ6: u32OTG_HS_DIEPDMA6: u32OTG_HS_DTXFSTS6: u32OTG_HS_DIEPCTL7: u32OTG_HS_DIEPINT7: u32OTG_HS_DIEPTSIZ7: u32OTG_HS_DIEPDMA7: u32OTG_HS_DTXFSTS7: u32OTG_HS_DIEPDMA8: u32OTG_HS_DIEPDMA9: u32OTG_HS_DIEPDMA10: u32OTG_HS_DIEPDMA11: u32OTG_HS_DIEPDMA12: u32OTG_HS_DIEPDMA13: u32OTG_HS_DIEPDMA14: u32OTG_HS_DIEPDMA15: u32OTG_HS_DOEPCTL0: u32OTG_HS_DOEPINT0: u32OTG_HS_DOEPTSIZ0: u32OTG_HS_DOEPDMA0: u32OTG_HS_DOEPCTL1: u32OTG_HS_DOEPINT1: u32OTG_HS_DOEPTSIZ1: u32OTG_HS_DOEPDMA1: u32OTG_HS_DOEPCTL2: u32OTG_HS_DOEPINT2: u32OTG_HS_DOEPTSIZ2: u32OTG_HS_DOEPDMA2: u32OTG_HS_DOEPCTL3: u32OTG_HS_DOEPINT3: u32OTG_HS_DOEPTSIZ3: u32OTG_HS_DOEPDMA3: u32OTG_HS_DOEPCTL4: u32OTG_HS_DOEPINT4: u32OTG_HS_DOEPTSIZ4: u32OTG_HS_DOEPDMA4: u32OTG_HS_DOEPCTL5: u32OTG_HS_DOEPINT5: u32OTG_HS_DOEPTSIZ5: u32OTG_HS_DOEPDMA5: u32OTG_HS_DOEPCTL6: u32OTG_HS_DOEPINT6: u32OTG_HS_DOEPTSIZ6: u32OTG_HS_DOEPDMA6: u32OTG_HS_DOEPCTL7: u32OTG_HS_DOEPINT7: u32OTG_HS_DOEPTSIZ7: u32OTG_HS_DOEPDMA7: u32OTG_HS_DOEPDMA8: u32OTG_HS_DOEPDMA9: u32OTG_HS_DOEPDMA10: u32OTG_HS_DOEPDMA11: u32OTG_HS_DOEPDMA12: u32OTG_HS_DOEPDMA13: u32OTG_HS_DOEPDMA14: u32OTG_HS_DOEPDMA15: u32