Struct stm32ral::stm32f4::stm32f413::dma::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 52 fields
pub LISR: RORegister<u32>,
pub HISR: RORegister<u32>,
pub LIFCR: WORegister<u32>,
pub HIFCR: WORegister<u32>,
pub CR0: RWRegister<u32>,
pub NDTR0: RWRegister<u32>,
pub PAR0: RWRegister<u32>,
pub M0AR0: RWRegister<u32>,
pub M1AR0: RWRegister<u32>,
pub FCR0: RWRegister<u32>,
pub CR1: RWRegister<u32>,
pub NDTR1: RWRegister<u32>,
pub PAR1: RWRegister<u32>,
pub M0AR1: RWRegister<u32>,
pub M1AR1: RWRegister<u32>,
pub FCR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub NDTR2: RWRegister<u32>,
pub PAR2: RWRegister<u32>,
pub M0AR2: RWRegister<u32>,
pub M1AR2: RWRegister<u32>,
pub FCR2: RWRegister<u32>,
pub CR3: RWRegister<u32>,
pub NDTR3: RWRegister<u32>,
pub PAR3: RWRegister<u32>,
pub M0AR3: RWRegister<u32>,
pub M1AR3: RWRegister<u32>,
pub FCR3: RWRegister<u32>,
pub CR4: RWRegister<u32>,
pub NDTR4: RWRegister<u32>,
pub PAR4: RWRegister<u32>,
pub M0AR4: RWRegister<u32>,
pub M1AR4: RWRegister<u32>,
pub FCR4: RWRegister<u32>,
pub CR5: RWRegister<u32>,
pub NDTR5: RWRegister<u32>,
pub PAR5: RWRegister<u32>,
pub M0AR5: RWRegister<u32>,
pub M1AR5: RWRegister<u32>,
pub FCR5: RWRegister<u32>,
pub CR6: RWRegister<u32>,
pub NDTR6: RWRegister<u32>,
pub PAR6: RWRegister<u32>,
pub M0AR6: RWRegister<u32>,
pub M1AR6: RWRegister<u32>,
pub FCR6: RWRegister<u32>,
pub CR7: RWRegister<u32>,
pub NDTR7: RWRegister<u32>,
pub PAR7: RWRegister<u32>,
pub M0AR7: RWRegister<u32>,
pub M1AR7: RWRegister<u32>,
pub FCR7: RWRegister<u32>,
}
Fields
LISR: RORegister<u32>
low interrupt status register
HISR: RORegister<u32>
high interrupt status register
LIFCR: WORegister<u32>
low interrupt flag clear register
HIFCR: WORegister<u32>
high interrupt flag clear register
CR0: RWRegister<u32>
stream x configuration register
NDTR0: RWRegister<u32>
stream x number of data register
PAR0: RWRegister<u32>
stream x peripheral address register
M0AR0: RWRegister<u32>
stream x memory 0 address register
M1AR0: RWRegister<u32>
stream x memory 1 address register
FCR0: RWRegister<u32>
stream x FIFO control register
CR1: RWRegister<u32>
stream x configuration register
NDTR1: RWRegister<u32>
stream x number of data register
PAR1: RWRegister<u32>
stream x peripheral address register
M0AR1: RWRegister<u32>
stream x memory 0 address register
M1AR1: RWRegister<u32>
stream x memory 1 address register
FCR1: RWRegister<u32>
stream x FIFO control register
CR2: RWRegister<u32>
stream x configuration register
NDTR2: RWRegister<u32>
stream x number of data register
PAR2: RWRegister<u32>
stream x peripheral address register
M0AR2: RWRegister<u32>
stream x memory 0 address register
M1AR2: RWRegister<u32>
stream x memory 1 address register
FCR2: RWRegister<u32>
stream x FIFO control register
CR3: RWRegister<u32>
stream x configuration register
NDTR3: RWRegister<u32>
stream x number of data register
PAR3: RWRegister<u32>
stream x peripheral address register
M0AR3: RWRegister<u32>
stream x memory 0 address register
M1AR3: RWRegister<u32>
stream x memory 1 address register
FCR3: RWRegister<u32>
stream x FIFO control register
CR4: RWRegister<u32>
stream x configuration register
NDTR4: RWRegister<u32>
stream x number of data register
PAR4: RWRegister<u32>
stream x peripheral address register
M0AR4: RWRegister<u32>
stream x memory 0 address register
M1AR4: RWRegister<u32>
stream x memory 1 address register
FCR4: RWRegister<u32>
stream x FIFO control register
CR5: RWRegister<u32>
stream x configuration register
NDTR5: RWRegister<u32>
stream x number of data register
PAR5: RWRegister<u32>
stream x peripheral address register
M0AR5: RWRegister<u32>
stream x memory 0 address register
M1AR5: RWRegister<u32>
stream x memory 1 address register
FCR5: RWRegister<u32>
stream x FIFO control register
CR6: RWRegister<u32>
stream x configuration register
NDTR6: RWRegister<u32>
stream x number of data register
PAR6: RWRegister<u32>
stream x peripheral address register
M0AR6: RWRegister<u32>
stream x memory 0 address register
M1AR6: RWRegister<u32>
stream x memory 1 address register
FCR6: RWRegister<u32>
stream x FIFO control register
CR7: RWRegister<u32>
stream x configuration register
NDTR7: RWRegister<u32>
stream x number of data register
PAR7: RWRegister<u32>
stream x peripheral address register
M0AR7: RWRegister<u32>
stream x memory 0 address register
M1AR7: RWRegister<u32>
stream x memory 1 address register
FCR7: RWRegister<u32>
stream x FIFO control register