Struct stm32ral::stm32f3::stm32f3x8::tim15::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 17 fields
pub CR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub SMCR: RWRegister<u32>,
pub DIER: RWRegister<u32>,
pub SR: RWRegister<u32>,
pub EGR: WORegister<u32>,
pub CCMR1: RWRegister<u32>,
pub CCER: RWRegister<u32>,
pub CNT: RWRegister<u32>,
pub PSC: RWRegister<u32>,
pub ARR: RWRegister<u32>,
pub RCR: RWRegister<u32>,
pub CCR1: RWRegister<u32>,
pub CCR2: RWRegister<u32>,
pub BDTR: RWRegister<u32>,
pub DCR: RWRegister<u32>,
pub DMAR: RWRegister<u32>,
// some fields omitted
}
Fields
CR1: RWRegister<u32>
control register 1
CR2: RWRegister<u32>
control register 2
SMCR: RWRegister<u32>
slave mode control register
DIER: RWRegister<u32>
DMA/Interrupt enable register
SR: RWRegister<u32>
status register
EGR: WORegister<u32>
event generation register
CCMR1: RWRegister<u32>
CCMR1_Output and CCMR1_Input CCMR1_Output: capture/compare mode register (output mode) CCMR1_Input: capture/compare mode register 1 (input mode)
CCER: RWRegister<u32>
capture/compare enable register
CNT: RWRegister<u32>
counter
PSC: RWRegister<u32>
prescaler
ARR: RWRegister<u32>
auto-reload register
RCR: RWRegister<u32>
repetition counter register
CCR1: RWRegister<u32>
capture/compare register 1
CCR2: RWRegister<u32>
capture/compare register 2
BDTR: RWRegister<u32>
break and dead-time register
DCR: RWRegister<u32>
DMA control register
DMAR: RWRegister<u32>
DMA address for full transfer