Struct stm32ral::stm32f2::peripherals::dma::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {Show 52 fields
    pub LISR: RORegister<u32>,
    pub HISR: RORegister<u32>,
    pub LIFCR: WORegister<u32>,
    pub HIFCR: WORegister<u32>,
    pub CR0: RWRegister<u32>,
    pub NDTR0: RWRegister<u32>,
    pub PAR0: RWRegister<u32>,
    pub M0AR0: RWRegister<u32>,
    pub M1AR0: RWRegister<u32>,
    pub FCR0: RWRegister<u32>,
    pub CR1: RWRegister<u32>,
    pub NDTR1: RWRegister<u32>,
    pub PAR1: RWRegister<u32>,
    pub M0AR1: RWRegister<u32>,
    pub M1AR1: RWRegister<u32>,
    pub FCR1: RWRegister<u32>,
    pub CR2: RWRegister<u32>,
    pub NDTR2: RWRegister<u32>,
    pub PAR2: RWRegister<u32>,
    pub M0AR2: RWRegister<u32>,
    pub M1AR2: RWRegister<u32>,
    pub FCR2: RWRegister<u32>,
    pub CR3: RWRegister<u32>,
    pub NDTR3: RWRegister<u32>,
    pub PAR3: RWRegister<u32>,
    pub M0AR3: RWRegister<u32>,
    pub M1AR3: RWRegister<u32>,
    pub FCR3: RWRegister<u32>,
    pub CR4: RWRegister<u32>,
    pub NDTR4: RWRegister<u32>,
    pub PAR4: RWRegister<u32>,
    pub M0AR4: RWRegister<u32>,
    pub M1AR4: RWRegister<u32>,
    pub FCR4: RWRegister<u32>,
    pub CR5: RWRegister<u32>,
    pub NDTR5: RWRegister<u32>,
    pub PAR5: RWRegister<u32>,
    pub M0AR5: RWRegister<u32>,
    pub M1AR5: RWRegister<u32>,
    pub FCR5: RWRegister<u32>,
    pub CR6: RWRegister<u32>,
    pub NDTR6: RWRegister<u32>,
    pub PAR6: RWRegister<u32>,
    pub M0AR6: RWRegister<u32>,
    pub M1AR6: RWRegister<u32>,
    pub FCR6: RWRegister<u32>,
    pub CR7: RWRegister<u32>,
    pub NDTR7: RWRegister<u32>,
    pub PAR7: RWRegister<u32>,
    pub M0AR7: RWRegister<u32>,
    pub M1AR7: RWRegister<u32>,
    pub FCR7: RWRegister<u32>,
}

Fields

LISR: RORegister<u32>

low interrupt status register

HISR: RORegister<u32>

high interrupt status register

LIFCR: WORegister<u32>

low interrupt flag clear register

HIFCR: WORegister<u32>

high interrupt flag clear register

CR0: RWRegister<u32>

stream x configuration register

NDTR0: RWRegister<u32>

stream x number of data register

PAR0: RWRegister<u32>

stream x peripheral address register

M0AR0: RWRegister<u32>

stream x memory 0 address register

M1AR0: RWRegister<u32>

stream x memory 1 address register

FCR0: RWRegister<u32>

stream x FIFO control register

CR1: RWRegister<u32>

stream x configuration register

NDTR1: RWRegister<u32>

stream x number of data register

PAR1: RWRegister<u32>

stream x peripheral address register

M0AR1: RWRegister<u32>

stream x memory 0 address register

M1AR1: RWRegister<u32>

stream x memory 1 address register

FCR1: RWRegister<u32>

stream x FIFO control register

CR2: RWRegister<u32>

stream x configuration register

NDTR2: RWRegister<u32>

stream x number of data register

PAR2: RWRegister<u32>

stream x peripheral address register

M0AR2: RWRegister<u32>

stream x memory 0 address register

M1AR2: RWRegister<u32>

stream x memory 1 address register

FCR2: RWRegister<u32>

stream x FIFO control register

CR3: RWRegister<u32>

stream x configuration register

NDTR3: RWRegister<u32>

stream x number of data register

PAR3: RWRegister<u32>

stream x peripheral address register

M0AR3: RWRegister<u32>

stream x memory 0 address register

M1AR3: RWRegister<u32>

stream x memory 1 address register

FCR3: RWRegister<u32>

stream x FIFO control register

CR4: RWRegister<u32>

stream x configuration register

NDTR4: RWRegister<u32>

stream x number of data register

PAR4: RWRegister<u32>

stream x peripheral address register

M0AR4: RWRegister<u32>

stream x memory 0 address register

M1AR4: RWRegister<u32>

stream x memory 1 address register

FCR4: RWRegister<u32>

stream x FIFO control register

CR5: RWRegister<u32>

stream x configuration register

NDTR5: RWRegister<u32>

stream x number of data register

PAR5: RWRegister<u32>

stream x peripheral address register

M0AR5: RWRegister<u32>

stream x memory 0 address register

M1AR5: RWRegister<u32>

stream x memory 1 address register

FCR5: RWRegister<u32>

stream x FIFO control register

CR6: RWRegister<u32>

stream x configuration register

NDTR6: RWRegister<u32>

stream x number of data register

PAR6: RWRegister<u32>

stream x peripheral address register

M0AR6: RWRegister<u32>

stream x memory 0 address register

M1AR6: RWRegister<u32>

stream x memory 1 address register

FCR6: RWRegister<u32>

stream x FIFO control register

CR7: RWRegister<u32>

stream x configuration register

NDTR7: RWRegister<u32>

stream x number of data register

PAR7: RWRegister<u32>

stream x peripheral address register

M0AR7: RWRegister<u32>

stream x memory 0 address register

M1AR7: RWRegister<u32>

stream x memory 1 address register

FCR7: RWRegister<u32>

stream x FIFO control register

Auto Trait Implementations

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations

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impl<T> Any for T where
T: 'static + ?Sized,

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pub fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

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impl<T> Borrow<T> for T where
T: ?Sized,

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pub fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

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impl<T> BorrowMut<T> for T where
T: ?Sized,

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pub fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

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impl<T> From<T> for T

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pub fn from(t: T) -> T

Performs the conversion.

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impl<T, U> Into for T where
U: From<T>,

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pub fn into(self) -> U

Performs the conversion.

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impl<T, U> TryFrom for T where
U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

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pub fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for T where
U: TryFrom<T>,

type Error = >::Error

The type returned in the event of a conversion error.

[src]

pub fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct stm32ral::stm32f2::peripherals::dma::RegisterBlock[−][src]

Fields

Auto Trait Implementations

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations

impl<T> Any for T where
T: 'static + ?Sized,

pub fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T where
T: ?Sized,

pub fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T where
T: ?Sized,

pub fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

pub fn from(t: T) -> T

impl<T, U> Into<U> for T where
U: From<T>,

pub fn into(self) -> U

impl<T, U> TryFrom<U> for T where
U: Into<T>,

type Error = Infallible

pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T where
U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

pub fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct stm32ral::stm32f2::peripherals::dma::RegisterBlock[−][src]

Fields

Auto Trait Implementations

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations

impl<T> Any for T where T: 'static + ?Sized,

pub fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T where T: ?Sized,

pub fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T where T: ?Sized,

pub fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

pub fn from(t: T) -> T

impl<T, U> Into<U> for T where U: From<T>,

pub fn into(self) -> U

impl<T, U> TryFrom<U> for T where U: Into<T>,

type Error = Infallible

pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

pub fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<T> Any for T where
T: 'static + ?Sized,

impl<T> Borrow<T> for T where
T: ?Sized,

impl<T> BorrowMut<T> for T where
T: ?Sized,

impl<T, U> Into<U> for T where
U: From<T>,

impl<T, U> TryFrom<U> for T where
U: Into<T>,

impl<T, U> TryInto<U> for T where
U: TryFrom<T>,