Module stm32mp1::stm32mp157::tim7
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TIM7
Modules
TIM7 auto-reload register
As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
TIM7 capture/compare enable register
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The channels 5 and 6 can only be configured in output. Output compare mode:
TIM7 capture/compare register 1
TIM7 capture/compare register 2
TIM7 capture/compare register 3
TIM7 capture/compare register 4
TIM7 capture/compare register 5
TIM7 capture/compare register 6
TIM7 counter
TIM7 control register 1
TIM7 control register 2
TIM7 DMA control register
TIM7 DMA/interrupt enable register
TIM7 DMA address for full transfer
TIM7 event generation register
TIM7 prescaler
TIM7 repetition counter register
TIM7 slave mode control register
TIM7 status register
Structs
Register block
Type Definitions
TIM7_ARR register accessor: an alias for Reg<TIM7_ARR_SPEC>
TIM7_BDTR register accessor: an alias for Reg<TIM7_BDTR_SPEC>
TIM7_CCER register accessor: an alias for Reg<TIM7_CCER_SPEC>
TIM7_CCMR1ALTERNATE7 register accessor: an alias for Reg<TIM7_CCMR1ALTERNATE7_SPEC>
TIM7_CCMR2ALTERNATE23 register accessor: an alias for Reg<TIM7_CCMR2ALTERNATE23_SPEC>
TIM7_CCMR3 register accessor: an alias for Reg<TIM7_CCMR3_SPEC>
TIM7_CCR1 register accessor: an alias for Reg<TIM7_CCR1_SPEC>
TIM7_CCR2 register accessor: an alias for Reg<TIM7_CCR2_SPEC>
TIM7_CCR3 register accessor: an alias for Reg<TIM7_CCR3_SPEC>
TIM7_CCR4 register accessor: an alias for Reg<TIM7_CCR4_SPEC>
TIM7_CCR5 register accessor: an alias for Reg<TIM7_CCR5_SPEC>
TIM7_CCR6 register accessor: an alias for Reg<TIM7_CCR6_SPEC>
TIM7_CNT register accessor: an alias for Reg<TIM7_CNT_SPEC>
TIM7_CR1 register accessor: an alias for Reg<TIM7_CR1_SPEC>
TIM7_CR2 register accessor: an alias for Reg<TIM7_CR2_SPEC>
TIM7_DCR register accessor: an alias for Reg<TIM7_DCR_SPEC>
TIM7_DIER register accessor: an alias for Reg<TIM7_DIER_SPEC>
TIM7_DMAR register accessor: an alias for Reg<TIM7_DMAR_SPEC>
TIM7_EGR register accessor: an alias for Reg<TIM7_EGR_SPEC>
TIM7_PSC register accessor: an alias for Reg<TIM7_PSC_SPEC>
TIM7_RCR register accessor: an alias for Reg<TIM7_RCR_SPEC>
TIM7_SMCR register accessor: an alias for Reg<TIM7_SMCR_SPEC>
TIM7_SR register accessor: an alias for Reg<TIM7_SR_SPEC>