Module stm32mp1::stm32mp157::tim3
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TIM3
Modules
TIM3 auto-reload register
As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
TIM3 capture/compare enable register
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The channels 5 and 6 can only be configured in output. Output compare mode:
TIM3 capture/compare register 1
TIM3 capture/compare register 2
TIM3 capture/compare register 3
TIM3 capture/compare register 4
TIM3 capture/compare register 5
TIM3 capture/compare register 6
TIM3 counter
TIM3 control register 1
TIM3 control register 2
TIM3 DMA control register
TIM3 DMA/interrupt enable register
TIM3 DMA address for full transfer
TIM3 event generation register
TIM3 prescaler
TIM3 repetition counter register
TIM3 slave mode control register
TIM3 status register
Structs
Register block
Type Definitions
TIM3_ARR register accessor: an alias for Reg<TIM3_ARR_SPEC>
TIM3_BDTR register accessor: an alias for Reg<TIM3_BDTR_SPEC>
TIM3_CCER register accessor: an alias for Reg<TIM3_CCER_SPEC>
TIM3_CCMR1ALTERNATE3 register accessor: an alias for Reg<TIM3_CCMR1ALTERNATE3_SPEC>
TIM3_CCMR2ALTERNATE19 register accessor: an alias for Reg<TIM3_CCMR2ALTERNATE19_SPEC>
TIM3_CCMR3 register accessor: an alias for Reg<TIM3_CCMR3_SPEC>
TIM3_CCR1 register accessor: an alias for Reg<TIM3_CCR1_SPEC>
TIM3_CCR2 register accessor: an alias for Reg<TIM3_CCR2_SPEC>
TIM3_CCR3 register accessor: an alias for Reg<TIM3_CCR3_SPEC>
TIM3_CCR4 register accessor: an alias for Reg<TIM3_CCR4_SPEC>
TIM3_CCR5 register accessor: an alias for Reg<TIM3_CCR5_SPEC>
TIM3_CCR6 register accessor: an alias for Reg<TIM3_CCR6_SPEC>
TIM3_CNT register accessor: an alias for Reg<TIM3_CNT_SPEC>
TIM3_CR1 register accessor: an alias for Reg<TIM3_CR1_SPEC>
TIM3_CR2 register accessor: an alias for Reg<TIM3_CR2_SPEC>
TIM3_DCR register accessor: an alias for Reg<TIM3_DCR_SPEC>
TIM3_DIER register accessor: an alias for Reg<TIM3_DIER_SPEC>
TIM3_DMAR register accessor: an alias for Reg<TIM3_DMAR_SPEC>
TIM3_EGR register accessor: an alias for Reg<TIM3_EGR_SPEC>
TIM3_PSC register accessor: an alias for Reg<TIM3_PSC_SPEC>
TIM3_RCR register accessor: an alias for Reg<TIM3_RCR_SPEC>
TIM3_SMCR register accessor: an alias for Reg<TIM3_SMCR_SPEC>
TIM3_SR register accessor: an alias for Reg<TIM3_SR_SPEC>