Module stm32mp1::stm32mp157::sdmmc1::sdmmc_fifor6

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Structs

R

Register SDMMC_FIFOR6 reader

SDMMC_FIFOR6_SPEC

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

W

Register SDMMC_FIFOR6 writer

Type Definitions

FIFODATA_R

Field FIFODATA reader - FIFODATA

FIFODATA_W

Field FIFODATA writer - FIFODATA