Expand description

MDMA1

Modules

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 0 error status register

MDMA channel 0 interrupt flag clear register

MDMA channel 0 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 1 error status register

MDMA channel 1 interrupt flag clear register

MDMA channel 1 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 2 error status register

MDMA channel 2 interrupt flag clear register

MDMA channel 2 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 3 error status register

MDMA channel 3 interrupt flag clear register

MDMA channel 3 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 4 error status register

MDMA channel 4 interrupt flag clear register

MDMA channel 4 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 5 error status register

MDMA channel 5 interrupt flag clear register

MDMA channel 5 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 6 error status register

MDMA channel 6 interrupt flag clear register

MDMA channel 6 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 7 error status register

MDMA channel 7 interrupt flag clear register

MDMA channel 7 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 8 error status register

MDMA channel 8 interrupt flag clear register

MDMA channel 8 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 9 error status register

MDMA channel 9 interrupt flag clear register

MDMA channel 9 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 10 error status register

MDMA channel 10 interrupt flag clear register

MDMA channel 10 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 11 error status register

MDMA channel 11 interrupt flag clear register

MDMA channel 11 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 12 error status register

MDMA channel 12 interrupt flag clear register

MDMA channel 12 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 13 error status register

MDMA channel 13 interrupt flag clear register

MDMA channel 13 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 14 error status register

MDMA channel 14 interrupt flag clear register

MDMA channel 14 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 15 error status register

MDMA channel 15 interrupt flag clear register

MDMA channel 15 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 16 error status register

MDMA channel 16 interrupt flag clear register

MDMA channel 16 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 17 error status register

MDMA channel 17 interrupt flag clear register

MDMA channel 17 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 18 error status register

MDMA channel 18 interrupt flag clear register

MDMA channel 18 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 19 error status register

MDMA channel 19 interrupt flag clear register

MDMA channel 19 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 20 error status register

MDMA channel 20 interrupt flag clear register

MDMA channel 20 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 21 error status register

MDMA channel 21 interrupt flag clear register

MDMA channel 21 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 22 error status register

MDMA channel 22 interrupt flag clear register

MDMA channel 22 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 23 error status register

MDMA channel 23 interrupt flag clear register

MDMA channel 23 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 24 error status register

MDMA channel 24 interrupt flag clear register

MDMA channel 24 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 25 error status register

MDMA channel 25 interrupt flag clear register

MDMA channel 25 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 26 error status register

MDMA channel 26 interrupt flag clear register

MDMA channel 26 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 27 error status register

MDMA channel 27 interrupt flag clear register

MDMA channel 27 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 28 error status register

MDMA channel 28 interrupt flag clear register

MDMA channel 28 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 29 error status register

MDMA channel 29 interrupt flag clear register

MDMA channel 29 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 30 error status register

MDMA channel 30 interrupt flag clear register

MDMA channel 30 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to control the concerned channel.

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA channel 31 error status register

MDMA channel 31 interrupt flag clear register

MDMA channel 31 interrupt/status register

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

MDMA global interrupt/status register

MDMA secure global interrupt/status register

Structs

Register block

Type Definitions

MDMA_C0BNDTR register accessor: an alias for Reg<MDMA_C0BNDTR_SPEC>

MDMA_C0BRUR register accessor: an alias for Reg<MDMA_C0BRUR_SPEC>

MDMA_C0CR register accessor: an alias for Reg<MDMA_C0CR_SPEC>

MDMA_C0DAR register accessor: an alias for Reg<MDMA_C0DAR_SPEC>

MDMA_C0ESR register accessor: an alias for Reg<MDMA_C0ESR_SPEC>

MDMA_C0IFCR register accessor: an alias for Reg<MDMA_C0IFCR_SPEC>

MDMA_C0ISR register accessor: an alias for Reg<MDMA_C0ISR_SPEC>

MDMA_C0LAR register accessor: an alias for Reg<MDMA_C0LAR_SPEC>

MDMA_C0MAR register accessor: an alias for Reg<MDMA_C0MAR_SPEC>

MDMA_C0MDR register accessor: an alias for Reg<MDMA_C0MDR_SPEC>

MDMA_C0SAR register accessor: an alias for Reg<MDMA_C0SAR_SPEC>

MDMA_C0TBR register accessor: an alias for Reg<MDMA_C0TBR_SPEC>

MDMA_C0TCR register accessor: an alias for Reg<MDMA_C0TCR_SPEC>

MDMA_C1BNDTR register accessor: an alias for Reg<MDMA_C1BNDTR_SPEC>

MDMA_C1BRUR register accessor: an alias for Reg<MDMA_C1BRUR_SPEC>

MDMA_C1CR register accessor: an alias for Reg<MDMA_C1CR_SPEC>

MDMA_C1DAR register accessor: an alias for Reg<MDMA_C1DAR_SPEC>

MDMA_C1ESR register accessor: an alias for Reg<MDMA_C1ESR_SPEC>

MDMA_C1IFCR register accessor: an alias for Reg<MDMA_C1IFCR_SPEC>

MDMA_C1ISR register accessor: an alias for Reg<MDMA_C1ISR_SPEC>

MDMA_C1LAR register accessor: an alias for Reg<MDMA_C1LAR_SPEC>

MDMA_C1MAR register accessor: an alias for Reg<MDMA_C1MAR_SPEC>

MDMA_C1MDR register accessor: an alias for Reg<MDMA_C1MDR_SPEC>

MDMA_C1SAR register accessor: an alias for Reg<MDMA_C1SAR_SPEC>

MDMA_C1TBR register accessor: an alias for Reg<MDMA_C1TBR_SPEC>

MDMA_C1TCR register accessor: an alias for Reg<MDMA_C1TCR_SPEC>

MDMA_C2BNDTR register accessor: an alias for Reg<MDMA_C2BNDTR_SPEC>

MDMA_C2BRUR register accessor: an alias for Reg<MDMA_C2BRUR_SPEC>

MDMA_C2CR register accessor: an alias for Reg<MDMA_C2CR_SPEC>

MDMA_C2DAR register accessor: an alias for Reg<MDMA_C2DAR_SPEC>

MDMA_C2ESR register accessor: an alias for Reg<MDMA_C2ESR_SPEC>

MDMA_C2IFCR register accessor: an alias for Reg<MDMA_C2IFCR_SPEC>

MDMA_C2ISR register accessor: an alias for Reg<MDMA_C2ISR_SPEC>

MDMA_C2LAR register accessor: an alias for Reg<MDMA_C2LAR_SPEC>

MDMA_C2MAR register accessor: an alias for Reg<MDMA_C2MAR_SPEC>

MDMA_C2MDR register accessor: an alias for Reg<MDMA_C2MDR_SPEC>

MDMA_C2SAR register accessor: an alias for Reg<MDMA_C2SAR_SPEC>

MDMA_C2TBR register accessor: an alias for Reg<MDMA_C2TBR_SPEC>

MDMA_C2TCR register accessor: an alias for Reg<MDMA_C2TCR_SPEC>

MDMA_C3BNDTR register accessor: an alias for Reg<MDMA_C3BNDTR_SPEC>

MDMA_C3BRUR register accessor: an alias for Reg<MDMA_C3BRUR_SPEC>

MDMA_C3CR register accessor: an alias for Reg<MDMA_C3CR_SPEC>

MDMA_C3DAR register accessor: an alias for Reg<MDMA_C3DAR_SPEC>

MDMA_C3ESR register accessor: an alias for Reg<MDMA_C3ESR_SPEC>

MDMA_C3IFCR register accessor: an alias for Reg<MDMA_C3IFCR_SPEC>

MDMA_C3ISR register accessor: an alias for Reg<MDMA_C3ISR_SPEC>

MDMA_C3LAR register accessor: an alias for Reg<MDMA_C3LAR_SPEC>

MDMA_C3MAR register accessor: an alias for Reg<MDMA_C3MAR_SPEC>

MDMA_C3MDR register accessor: an alias for Reg<MDMA_C3MDR_SPEC>

MDMA_C3SAR register accessor: an alias for Reg<MDMA_C3SAR_SPEC>

MDMA_C3TBR register accessor: an alias for Reg<MDMA_C3TBR_SPEC>

MDMA_C3TCR register accessor: an alias for Reg<MDMA_C3TCR_SPEC>

MDMA_C4BNDTR register accessor: an alias for Reg<MDMA_C4BNDTR_SPEC>

MDMA_C4BRUR register accessor: an alias for Reg<MDMA_C4BRUR_SPEC>

MDMA_C4CR register accessor: an alias for Reg<MDMA_C4CR_SPEC>

MDMA_C4DAR register accessor: an alias for Reg<MDMA_C4DAR_SPEC>

MDMA_C4ESR register accessor: an alias for Reg<MDMA_C4ESR_SPEC>

MDMA_C4IFCR register accessor: an alias for Reg<MDMA_C4IFCR_SPEC>

MDMA_C4ISR register accessor: an alias for Reg<MDMA_C4ISR_SPEC>

MDMA_C4LAR register accessor: an alias for Reg<MDMA_C4LAR_SPEC>

MDMA_C4MAR register accessor: an alias for Reg<MDMA_C4MAR_SPEC>

MDMA_C4MDR register accessor: an alias for Reg<MDMA_C4MDR_SPEC>

MDMA_C4SAR register accessor: an alias for Reg<MDMA_C4SAR_SPEC>

MDMA_C4TBR register accessor: an alias for Reg<MDMA_C4TBR_SPEC>

MDMA_C4TCR register accessor: an alias for Reg<MDMA_C4TCR_SPEC>

MDMA_C5BNDTR register accessor: an alias for Reg<MDMA_C5BNDTR_SPEC>

MDMA_C5BRUR register accessor: an alias for Reg<MDMA_C5BRUR_SPEC>

MDMA_C5CR register accessor: an alias for Reg<MDMA_C5CR_SPEC>

MDMA_C5DAR register accessor: an alias for Reg<MDMA_C5DAR_SPEC>

MDMA_C5ESR register accessor: an alias for Reg<MDMA_C5ESR_SPEC>

MDMA_C5IFCR register accessor: an alias for Reg<MDMA_C5IFCR_SPEC>

MDMA_C5ISR register accessor: an alias for Reg<MDMA_C5ISR_SPEC>

MDMA_C5LAR register accessor: an alias for Reg<MDMA_C5LAR_SPEC>

MDMA_C5MAR register accessor: an alias for Reg<MDMA_C5MAR_SPEC>

MDMA_C5MDR register accessor: an alias for Reg<MDMA_C5MDR_SPEC>

MDMA_C5SAR register accessor: an alias for Reg<MDMA_C5SAR_SPEC>

MDMA_C5TBR register accessor: an alias for Reg<MDMA_C5TBR_SPEC>

MDMA_C5TCR register accessor: an alias for Reg<MDMA_C5TCR_SPEC>

MDMA_C6BNDTR register accessor: an alias for Reg<MDMA_C6BNDTR_SPEC>

MDMA_C6BRUR register accessor: an alias for Reg<MDMA_C6BRUR_SPEC>

MDMA_C6CR register accessor: an alias for Reg<MDMA_C6CR_SPEC>

MDMA_C6DAR register accessor: an alias for Reg<MDMA_C6DAR_SPEC>

MDMA_C6ESR register accessor: an alias for Reg<MDMA_C6ESR_SPEC>

MDMA_C6IFCR register accessor: an alias for Reg<MDMA_C6IFCR_SPEC>

MDMA_C6ISR register accessor: an alias for Reg<MDMA_C6ISR_SPEC>

MDMA_C6LAR register accessor: an alias for Reg<MDMA_C6LAR_SPEC>

MDMA_C6MAR register accessor: an alias for Reg<MDMA_C6MAR_SPEC>

MDMA_C6MDR register accessor: an alias for Reg<MDMA_C6MDR_SPEC>

MDMA_C6SAR register accessor: an alias for Reg<MDMA_C6SAR_SPEC>

MDMA_C6TBR register accessor: an alias for Reg<MDMA_C6TBR_SPEC>

MDMA_C6TCR register accessor: an alias for Reg<MDMA_C6TCR_SPEC>

MDMA_C7BNDTR register accessor: an alias for Reg<MDMA_C7BNDTR_SPEC>

MDMA_C7BRUR register accessor: an alias for Reg<MDMA_C7BRUR_SPEC>

MDMA_C7CR register accessor: an alias for Reg<MDMA_C7CR_SPEC>

MDMA_C7DAR register accessor: an alias for Reg<MDMA_C7DAR_SPEC>

MDMA_C7ESR register accessor: an alias for Reg<MDMA_C7ESR_SPEC>

MDMA_C7IFCR register accessor: an alias for Reg<MDMA_C7IFCR_SPEC>

MDMA_C7ISR register accessor: an alias for Reg<MDMA_C7ISR_SPEC>

MDMA_C7LAR register accessor: an alias for Reg<MDMA_C7LAR_SPEC>

MDMA_C7MAR register accessor: an alias for Reg<MDMA_C7MAR_SPEC>

MDMA_C7MDR register accessor: an alias for Reg<MDMA_C7MDR_SPEC>

MDMA_C7SAR register accessor: an alias for Reg<MDMA_C7SAR_SPEC>

MDMA_C7TBR register accessor: an alias for Reg<MDMA_C7TBR_SPEC>

MDMA_C7TCR register accessor: an alias for Reg<MDMA_C7TCR_SPEC>

MDMA_C8BNDTR register accessor: an alias for Reg<MDMA_C8BNDTR_SPEC>

MDMA_C8BRUR register accessor: an alias for Reg<MDMA_C8BRUR_SPEC>

MDMA_C8CR register accessor: an alias for Reg<MDMA_C8CR_SPEC>

MDMA_C8DAR register accessor: an alias for Reg<MDMA_C8DAR_SPEC>

MDMA_C8ESR register accessor: an alias for Reg<MDMA_C8ESR_SPEC>

MDMA_C8IFCR register accessor: an alias for Reg<MDMA_C8IFCR_SPEC>

MDMA_C8ISR register accessor: an alias for Reg<MDMA_C8ISR_SPEC>

MDMA_C8LAR register accessor: an alias for Reg<MDMA_C8LAR_SPEC>

MDMA_C8MAR register accessor: an alias for Reg<MDMA_C8MAR_SPEC>

MDMA_C8MDR register accessor: an alias for Reg<MDMA_C8MDR_SPEC>

MDMA_C8SAR register accessor: an alias for Reg<MDMA_C8SAR_SPEC>

MDMA_C8TBR register accessor: an alias for Reg<MDMA_C8TBR_SPEC>

MDMA_C8TCR register accessor: an alias for Reg<MDMA_C8TCR_SPEC>

MDMA_C9BNDTR register accessor: an alias for Reg<MDMA_C9BNDTR_SPEC>

MDMA_C9BRUR register accessor: an alias for Reg<MDMA_C9BRUR_SPEC>

MDMA_C9CR register accessor: an alias for Reg<MDMA_C9CR_SPEC>

MDMA_C9DAR register accessor: an alias for Reg<MDMA_C9DAR_SPEC>

MDMA_C9ESR register accessor: an alias for Reg<MDMA_C9ESR_SPEC>

MDMA_C9IFCR register accessor: an alias for Reg<MDMA_C9IFCR_SPEC>

MDMA_C9ISR register accessor: an alias for Reg<MDMA_C9ISR_SPEC>

MDMA_C9LAR register accessor: an alias for Reg<MDMA_C9LAR_SPEC>

MDMA_C9MAR register accessor: an alias for Reg<MDMA_C9MAR_SPEC>

MDMA_C9MDR register accessor: an alias for Reg<MDMA_C9MDR_SPEC>

MDMA_C9SAR register accessor: an alias for Reg<MDMA_C9SAR_SPEC>

MDMA_C9TBR register accessor: an alias for Reg<MDMA_C9TBR_SPEC>

MDMA_C9TCR register accessor: an alias for Reg<MDMA_C9TCR_SPEC>

MDMA_C10BNDTR register accessor: an alias for Reg<MDMA_C10BNDTR_SPEC>

MDMA_C10BRUR register accessor: an alias for Reg<MDMA_C10BRUR_SPEC>

MDMA_C10CR register accessor: an alias for Reg<MDMA_C10CR_SPEC>

MDMA_C10DAR register accessor: an alias for Reg<MDMA_C10DAR_SPEC>

MDMA_C10ESR register accessor: an alias for Reg<MDMA_C10ESR_SPEC>

MDMA_C10IFCR register accessor: an alias for Reg<MDMA_C10IFCR_SPEC>

MDMA_C10ISR register accessor: an alias for Reg<MDMA_C10ISR_SPEC>

MDMA_C10LAR register accessor: an alias for Reg<MDMA_C10LAR_SPEC>

MDMA_C10MAR register accessor: an alias for Reg<MDMA_C10MAR_SPEC>

MDMA_C10MDR register accessor: an alias for Reg<MDMA_C10MDR_SPEC>

MDMA_C10SAR register accessor: an alias for Reg<MDMA_C10SAR_SPEC>

MDMA_C10TBR register accessor: an alias for Reg<MDMA_C10TBR_SPEC>

MDMA_C10TCR register accessor: an alias for Reg<MDMA_C10TCR_SPEC>

MDMA_C11BNDTR register accessor: an alias for Reg<MDMA_C11BNDTR_SPEC>

MDMA_C11BRUR register accessor: an alias for Reg<MDMA_C11BRUR_SPEC>

MDMA_C11CR register accessor: an alias for Reg<MDMA_C11CR_SPEC>

MDMA_C11DAR register accessor: an alias for Reg<MDMA_C11DAR_SPEC>

MDMA_C11ESR register accessor: an alias for Reg<MDMA_C11ESR_SPEC>

MDMA_C11IFCR register accessor: an alias for Reg<MDMA_C11IFCR_SPEC>

MDMA_C11ISR register accessor: an alias for Reg<MDMA_C11ISR_SPEC>

MDMA_C11LAR register accessor: an alias for Reg<MDMA_C11LAR_SPEC>

MDMA_C11MAR register accessor: an alias for Reg<MDMA_C11MAR_SPEC>

MDMA_C11MDR register accessor: an alias for Reg<MDMA_C11MDR_SPEC>

MDMA_C11SAR register accessor: an alias for Reg<MDMA_C11SAR_SPEC>

MDMA_C11TBR register accessor: an alias for Reg<MDMA_C11TBR_SPEC>

MDMA_C11TCR register accessor: an alias for Reg<MDMA_C11TCR_SPEC>

MDMA_C12BNDTR register accessor: an alias for Reg<MDMA_C12BNDTR_SPEC>

MDMA_C12BRUR register accessor: an alias for Reg<MDMA_C12BRUR_SPEC>

MDMA_C12CR register accessor: an alias for Reg<MDMA_C12CR_SPEC>

MDMA_C12DAR register accessor: an alias for Reg<MDMA_C12DAR_SPEC>

MDMA_C12ESR register accessor: an alias for Reg<MDMA_C12ESR_SPEC>

MDMA_C12IFCR register accessor: an alias for Reg<MDMA_C12IFCR_SPEC>

MDMA_C12ISR register accessor: an alias for Reg<MDMA_C12ISR_SPEC>

MDMA_C12LAR register accessor: an alias for Reg<MDMA_C12LAR_SPEC>

MDMA_C12MAR register accessor: an alias for Reg<MDMA_C12MAR_SPEC>

MDMA_C12MDR register accessor: an alias for Reg<MDMA_C12MDR_SPEC>

MDMA_C12SAR register accessor: an alias for Reg<MDMA_C12SAR_SPEC>

MDMA_C12TBR register accessor: an alias for Reg<MDMA_C12TBR_SPEC>

MDMA_C12TCR register accessor: an alias for Reg<MDMA_C12TCR_SPEC>

MDMA_C13BNDTR register accessor: an alias for Reg<MDMA_C13BNDTR_SPEC>

MDMA_C13BRUR register accessor: an alias for Reg<MDMA_C13BRUR_SPEC>

MDMA_C13CR register accessor: an alias for Reg<MDMA_C13CR_SPEC>

MDMA_C13DAR register accessor: an alias for Reg<MDMA_C13DAR_SPEC>

MDMA_C13ESR register accessor: an alias for Reg<MDMA_C13ESR_SPEC>

MDMA_C13IFCR register accessor: an alias for Reg<MDMA_C13IFCR_SPEC>

MDMA_C13ISR register accessor: an alias for Reg<MDMA_C13ISR_SPEC>

MDMA_C13LAR register accessor: an alias for Reg<MDMA_C13LAR_SPEC>

MDMA_C13MAR register accessor: an alias for Reg<MDMA_C13MAR_SPEC>

MDMA_C13MDR register accessor: an alias for Reg<MDMA_C13MDR_SPEC>

MDMA_C13SAR register accessor: an alias for Reg<MDMA_C13SAR_SPEC>

MDMA_C13TBR register accessor: an alias for Reg<MDMA_C13TBR_SPEC>

MDMA_C13TCR register accessor: an alias for Reg<MDMA_C13TCR_SPEC>

MDMA_C14BNDTR register accessor: an alias for Reg<MDMA_C14BNDTR_SPEC>

MDMA_C14BRUR register accessor: an alias for Reg<MDMA_C14BRUR_SPEC>

MDMA_C14CR register accessor: an alias for Reg<MDMA_C14CR_SPEC>

MDMA_C14DAR register accessor: an alias for Reg<MDMA_C14DAR_SPEC>

MDMA_C14ESR register accessor: an alias for Reg<MDMA_C14ESR_SPEC>

MDMA_C14IFCR register accessor: an alias for Reg<MDMA_C14IFCR_SPEC>

MDMA_C14ISR register accessor: an alias for Reg<MDMA_C14ISR_SPEC>

MDMA_C14LAR register accessor: an alias for Reg<MDMA_C14LAR_SPEC>

MDMA_C14MAR register accessor: an alias for Reg<MDMA_C14MAR_SPEC>

MDMA_C14MDR register accessor: an alias for Reg<MDMA_C14MDR_SPEC>

MDMA_C14SAR register accessor: an alias for Reg<MDMA_C14SAR_SPEC>

MDMA_C14TBR register accessor: an alias for Reg<MDMA_C14TBR_SPEC>

MDMA_C14TCR register accessor: an alias for Reg<MDMA_C14TCR_SPEC>

MDMA_C15BNDTR register accessor: an alias for Reg<MDMA_C15BNDTR_SPEC>

MDMA_C15BRUR register accessor: an alias for Reg<MDMA_C15BRUR_SPEC>

MDMA_C15CR register accessor: an alias for Reg<MDMA_C15CR_SPEC>

MDMA_C15DAR register accessor: an alias for Reg<MDMA_C15DAR_SPEC>

MDMA_C15ESR register accessor: an alias for Reg<MDMA_C15ESR_SPEC>

MDMA_C15IFCR register accessor: an alias for Reg<MDMA_C15IFCR_SPEC>

MDMA_C15ISR register accessor: an alias for Reg<MDMA_C15ISR_SPEC>

MDMA_C15LAR register accessor: an alias for Reg<MDMA_C15LAR_SPEC>

MDMA_C15MAR register accessor: an alias for Reg<MDMA_C15MAR_SPEC>

MDMA_C15MDR register accessor: an alias for Reg<MDMA_C15MDR_SPEC>

MDMA_C15SAR register accessor: an alias for Reg<MDMA_C15SAR_SPEC>

MDMA_C15TBR register accessor: an alias for Reg<MDMA_C15TBR_SPEC>

MDMA_C15TCR register accessor: an alias for Reg<MDMA_C15TCR_SPEC>

MDMA_C16BNDTR register accessor: an alias for Reg<MDMA_C16BNDTR_SPEC>

MDMA_C16BRUR register accessor: an alias for Reg<MDMA_C16BRUR_SPEC>

MDMA_C16CR register accessor: an alias for Reg<MDMA_C16CR_SPEC>

MDMA_C16DAR register accessor: an alias for Reg<MDMA_C16DAR_SPEC>

MDMA_C16ESR register accessor: an alias for Reg<MDMA_C16ESR_SPEC>

MDMA_C16IFCR register accessor: an alias for Reg<MDMA_C16IFCR_SPEC>

MDMA_C16ISR register accessor: an alias for Reg<MDMA_C16ISR_SPEC>

MDMA_C16LAR register accessor: an alias for Reg<MDMA_C16LAR_SPEC>

MDMA_C16MAR register accessor: an alias for Reg<MDMA_C16MAR_SPEC>

MDMA_C16MDR register accessor: an alias for Reg<MDMA_C16MDR_SPEC>

MDMA_C16SAR register accessor: an alias for Reg<MDMA_C16SAR_SPEC>

MDMA_C16TBR register accessor: an alias for Reg<MDMA_C16TBR_SPEC>

MDMA_C16TCR register accessor: an alias for Reg<MDMA_C16TCR_SPEC>

MDMA_C17BNDTR register accessor: an alias for Reg<MDMA_C17BNDTR_SPEC>

MDMA_C17BRUR register accessor: an alias for Reg<MDMA_C17BRUR_SPEC>

MDMA_C17CR register accessor: an alias for Reg<MDMA_C17CR_SPEC>

MDMA_C17DAR register accessor: an alias for Reg<MDMA_C17DAR_SPEC>

MDMA_C17ESR register accessor: an alias for Reg<MDMA_C17ESR_SPEC>

MDMA_C17IFCR register accessor: an alias for Reg<MDMA_C17IFCR_SPEC>

MDMA_C17ISR register accessor: an alias for Reg<MDMA_C17ISR_SPEC>

MDMA_C17LAR register accessor: an alias for Reg<MDMA_C17LAR_SPEC>

MDMA_C17MAR register accessor: an alias for Reg<MDMA_C17MAR_SPEC>

MDMA_C17MDR register accessor: an alias for Reg<MDMA_C17MDR_SPEC>

MDMA_C17SAR register accessor: an alias for Reg<MDMA_C17SAR_SPEC>

MDMA_C17TBR register accessor: an alias for Reg<MDMA_C17TBR_SPEC>

MDMA_C17TCR register accessor: an alias for Reg<MDMA_C17TCR_SPEC>

MDMA_C18BNDTR register accessor: an alias for Reg<MDMA_C18BNDTR_SPEC>

MDMA_C18BRUR register accessor: an alias for Reg<MDMA_C18BRUR_SPEC>

MDMA_C18CR register accessor: an alias for Reg<MDMA_C18CR_SPEC>

MDMA_C18DAR register accessor: an alias for Reg<MDMA_C18DAR_SPEC>

MDMA_C18ESR register accessor: an alias for Reg<MDMA_C18ESR_SPEC>

MDMA_C18IFCR register accessor: an alias for Reg<MDMA_C18IFCR_SPEC>

MDMA_C18ISR register accessor: an alias for Reg<MDMA_C18ISR_SPEC>

MDMA_C18LAR register accessor: an alias for Reg<MDMA_C18LAR_SPEC>

MDMA_C18MAR register accessor: an alias for Reg<MDMA_C18MAR_SPEC>

MDMA_C18MDR register accessor: an alias for Reg<MDMA_C18MDR_SPEC>

MDMA_C18SAR register accessor: an alias for Reg<MDMA_C18SAR_SPEC>

MDMA_C18TBR register accessor: an alias for Reg<MDMA_C18TBR_SPEC>

MDMA_C18TCR register accessor: an alias for Reg<MDMA_C18TCR_SPEC>

MDMA_C19BNDTR register accessor: an alias for Reg<MDMA_C19BNDTR_SPEC>

MDMA_C19BRUR register accessor: an alias for Reg<MDMA_C19BRUR_SPEC>

MDMA_C19CR register accessor: an alias for Reg<MDMA_C19CR_SPEC>

MDMA_C19DAR register accessor: an alias for Reg<MDMA_C19DAR_SPEC>

MDMA_C19ESR register accessor: an alias for Reg<MDMA_C19ESR_SPEC>

MDMA_C19IFCR register accessor: an alias for Reg<MDMA_C19IFCR_SPEC>

MDMA_C19ISR register accessor: an alias for Reg<MDMA_C19ISR_SPEC>

MDMA_C19LAR register accessor: an alias for Reg<MDMA_C19LAR_SPEC>

MDMA_C19MAR register accessor: an alias for Reg<MDMA_C19MAR_SPEC>

MDMA_C19MDR register accessor: an alias for Reg<MDMA_C19MDR_SPEC>

MDMA_C19SAR register accessor: an alias for Reg<MDMA_C19SAR_SPEC>

MDMA_C19TBR register accessor: an alias for Reg<MDMA_C19TBR_SPEC>

MDMA_C19TCR register accessor: an alias for Reg<MDMA_C19TCR_SPEC>

MDMA_C20BNDTR register accessor: an alias for Reg<MDMA_C20BNDTR_SPEC>

MDMA_C20BRUR register accessor: an alias for Reg<MDMA_C20BRUR_SPEC>

MDMA_C20CR register accessor: an alias for Reg<MDMA_C20CR_SPEC>

MDMA_C20DAR register accessor: an alias for Reg<MDMA_C20DAR_SPEC>

MDMA_C20ESR register accessor: an alias for Reg<MDMA_C20ESR_SPEC>

MDMA_C20IFCR register accessor: an alias for Reg<MDMA_C20IFCR_SPEC>

MDMA_C20ISR register accessor: an alias for Reg<MDMA_C20ISR_SPEC>

MDMA_C20LAR register accessor: an alias for Reg<MDMA_C20LAR_SPEC>

MDMA_C20MAR register accessor: an alias for Reg<MDMA_C20MAR_SPEC>

MDMA_C20MDR register accessor: an alias for Reg<MDMA_C20MDR_SPEC>

MDMA_C20SAR register accessor: an alias for Reg<MDMA_C20SAR_SPEC>

MDMA_C20TBR register accessor: an alias for Reg<MDMA_C20TBR_SPEC>

MDMA_C20TCR register accessor: an alias for Reg<MDMA_C20TCR_SPEC>

MDMA_C21BNDTR register accessor: an alias for Reg<MDMA_C21BNDTR_SPEC>

MDMA_C21BRUR register accessor: an alias for Reg<MDMA_C21BRUR_SPEC>

MDMA_C21CR register accessor: an alias for Reg<MDMA_C21CR_SPEC>

MDMA_C21DAR register accessor: an alias for Reg<MDMA_C21DAR_SPEC>

MDMA_C21ESR register accessor: an alias for Reg<MDMA_C21ESR_SPEC>

MDMA_C21IFCR register accessor: an alias for Reg<MDMA_C21IFCR_SPEC>

MDMA_C21ISR register accessor: an alias for Reg<MDMA_C21ISR_SPEC>

MDMA_C21LAR register accessor: an alias for Reg<MDMA_C21LAR_SPEC>

MDMA_C21MAR register accessor: an alias for Reg<MDMA_C21MAR_SPEC>

MDMA_C21MDR register accessor: an alias for Reg<MDMA_C21MDR_SPEC>

MDMA_C21SAR register accessor: an alias for Reg<MDMA_C21SAR_SPEC>

MDMA_C21TBR register accessor: an alias for Reg<MDMA_C21TBR_SPEC>

MDMA_C21TCR register accessor: an alias for Reg<MDMA_C21TCR_SPEC>

MDMA_C22BNDTR register accessor: an alias for Reg<MDMA_C22BNDTR_SPEC>

MDMA_C22BRUR register accessor: an alias for Reg<MDMA_C22BRUR_SPEC>

MDMA_C22CR register accessor: an alias for Reg<MDMA_C22CR_SPEC>

MDMA_C22DAR register accessor: an alias for Reg<MDMA_C22DAR_SPEC>

MDMA_C22ESR register accessor: an alias for Reg<MDMA_C22ESR_SPEC>

MDMA_C22IFCR register accessor: an alias for Reg<MDMA_C22IFCR_SPEC>

MDMA_C22ISR register accessor: an alias for Reg<MDMA_C22ISR_SPEC>

MDMA_C22LAR register accessor: an alias for Reg<MDMA_C22LAR_SPEC>

MDMA_C22MAR register accessor: an alias for Reg<MDMA_C22MAR_SPEC>

MDMA_C22MDR register accessor: an alias for Reg<MDMA_C22MDR_SPEC>

MDMA_C22SAR register accessor: an alias for Reg<MDMA_C22SAR_SPEC>

MDMA_C22TBR register accessor: an alias for Reg<MDMA_C22TBR_SPEC>

MDMA_C22TCR register accessor: an alias for Reg<MDMA_C22TCR_SPEC>

MDMA_C23BNDTR register accessor: an alias for Reg<MDMA_C23BNDTR_SPEC>

MDMA_C23BRUR register accessor: an alias for Reg<MDMA_C23BRUR_SPEC>

MDMA_C23CR register accessor: an alias for Reg<MDMA_C23CR_SPEC>

MDMA_C23DAR register accessor: an alias for Reg<MDMA_C23DAR_SPEC>

MDMA_C23ESR register accessor: an alias for Reg<MDMA_C23ESR_SPEC>

MDMA_C23IFCR register accessor: an alias for Reg<MDMA_C23IFCR_SPEC>

MDMA_C23ISR register accessor: an alias for Reg<MDMA_C23ISR_SPEC>

MDMA_C23LAR register accessor: an alias for Reg<MDMA_C23LAR_SPEC>

MDMA_C23MAR register accessor: an alias for Reg<MDMA_C23MAR_SPEC>

MDMA_C23MDR register accessor: an alias for Reg<MDMA_C23MDR_SPEC>

MDMA_C23SAR register accessor: an alias for Reg<MDMA_C23SAR_SPEC>

MDMA_C23TBR register accessor: an alias for Reg<MDMA_C23TBR_SPEC>

MDMA_C23TCR register accessor: an alias for Reg<MDMA_C23TCR_SPEC>

MDMA_C24BNDTR register accessor: an alias for Reg<MDMA_C24BNDTR_SPEC>

MDMA_C24BRUR register accessor: an alias for Reg<MDMA_C24BRUR_SPEC>

MDMA_C24CR register accessor: an alias for Reg<MDMA_C24CR_SPEC>

MDMA_C24DAR register accessor: an alias for Reg<MDMA_C24DAR_SPEC>

MDMA_C24ESR register accessor: an alias for Reg<MDMA_C24ESR_SPEC>

MDMA_C24IFCR register accessor: an alias for Reg<MDMA_C24IFCR_SPEC>

MDMA_C24ISR register accessor: an alias for Reg<MDMA_C24ISR_SPEC>

MDMA_C24LAR register accessor: an alias for Reg<MDMA_C24LAR_SPEC>

MDMA_C24MAR register accessor: an alias for Reg<MDMA_C24MAR_SPEC>

MDMA_C24MDR register accessor: an alias for Reg<MDMA_C24MDR_SPEC>

MDMA_C24SAR register accessor: an alias for Reg<MDMA_C24SAR_SPEC>

MDMA_C24TBR register accessor: an alias for Reg<MDMA_C24TBR_SPEC>

MDMA_C24TCR register accessor: an alias for Reg<MDMA_C24TCR_SPEC>

MDMA_C25BNDTR register accessor: an alias for Reg<MDMA_C25BNDTR_SPEC>

MDMA_C25BRUR register accessor: an alias for Reg<MDMA_C25BRUR_SPEC>

MDMA_C25CR register accessor: an alias for Reg<MDMA_C25CR_SPEC>

MDMA_C25DAR register accessor: an alias for Reg<MDMA_C25DAR_SPEC>

MDMA_C25ESR register accessor: an alias for Reg<MDMA_C25ESR_SPEC>

MDMA_C25IFCR register accessor: an alias for Reg<MDMA_C25IFCR_SPEC>

MDMA_C25ISR register accessor: an alias for Reg<MDMA_C25ISR_SPEC>

MDMA_C25LAR register accessor: an alias for Reg<MDMA_C25LAR_SPEC>

MDMA_C25MAR register accessor: an alias for Reg<MDMA_C25MAR_SPEC>

MDMA_C25MDR register accessor: an alias for Reg<MDMA_C25MDR_SPEC>

MDMA_C25SAR register accessor: an alias for Reg<MDMA_C25SAR_SPEC>

MDMA_C25TBR register accessor: an alias for Reg<MDMA_C25TBR_SPEC>

MDMA_C25TCR register accessor: an alias for Reg<MDMA_C25TCR_SPEC>

MDMA_C26BNDTR register accessor: an alias for Reg<MDMA_C26BNDTR_SPEC>

MDMA_C26BRUR register accessor: an alias for Reg<MDMA_C26BRUR_SPEC>

MDMA_C26CR register accessor: an alias for Reg<MDMA_C26CR_SPEC>

MDMA_C26DAR register accessor: an alias for Reg<MDMA_C26DAR_SPEC>

MDMA_C26ESR register accessor: an alias for Reg<MDMA_C26ESR_SPEC>

MDMA_C26IFCR register accessor: an alias for Reg<MDMA_C26IFCR_SPEC>

MDMA_C26ISR register accessor: an alias for Reg<MDMA_C26ISR_SPEC>

MDMA_C26LAR register accessor: an alias for Reg<MDMA_C26LAR_SPEC>

MDMA_C26MAR register accessor: an alias for Reg<MDMA_C26MAR_SPEC>

MDMA_C26MDR register accessor: an alias for Reg<MDMA_C26MDR_SPEC>

MDMA_C26SAR register accessor: an alias for Reg<MDMA_C26SAR_SPEC>

MDMA_C26TBR register accessor: an alias for Reg<MDMA_C26TBR_SPEC>

MDMA_C26TCR register accessor: an alias for Reg<MDMA_C26TCR_SPEC>

MDMA_C27BNDTR register accessor: an alias for Reg<MDMA_C27BNDTR_SPEC>

MDMA_C27BRUR register accessor: an alias for Reg<MDMA_C27BRUR_SPEC>

MDMA_C27CR register accessor: an alias for Reg<MDMA_C27CR_SPEC>

MDMA_C27DAR register accessor: an alias for Reg<MDMA_C27DAR_SPEC>

MDMA_C27ESR register accessor: an alias for Reg<MDMA_C27ESR_SPEC>

MDMA_C27IFCR register accessor: an alias for Reg<MDMA_C27IFCR_SPEC>

MDMA_C27ISR register accessor: an alias for Reg<MDMA_C27ISR_SPEC>

MDMA_C27LAR register accessor: an alias for Reg<MDMA_C27LAR_SPEC>

MDMA_C27MAR register accessor: an alias for Reg<MDMA_C27MAR_SPEC>

MDMA_C27MDR register accessor: an alias for Reg<MDMA_C27MDR_SPEC>

MDMA_C27SAR register accessor: an alias for Reg<MDMA_C27SAR_SPEC>

MDMA_C27TBR register accessor: an alias for Reg<MDMA_C27TBR_SPEC>

MDMA_C27TCR register accessor: an alias for Reg<MDMA_C27TCR_SPEC>

MDMA_C28BNDTR register accessor: an alias for Reg<MDMA_C28BNDTR_SPEC>

MDMA_C28BRUR register accessor: an alias for Reg<MDMA_C28BRUR_SPEC>

MDMA_C28CR register accessor: an alias for Reg<MDMA_C28CR_SPEC>

MDMA_C28DAR register accessor: an alias for Reg<MDMA_C28DAR_SPEC>

MDMA_C28ESR register accessor: an alias for Reg<MDMA_C28ESR_SPEC>

MDMA_C28IFCR register accessor: an alias for Reg<MDMA_C28IFCR_SPEC>

MDMA_C28ISR register accessor: an alias for Reg<MDMA_C28ISR_SPEC>

MDMA_C28LAR register accessor: an alias for Reg<MDMA_C28LAR_SPEC>

MDMA_C28MAR register accessor: an alias for Reg<MDMA_C28MAR_SPEC>

MDMA_C28MDR register accessor: an alias for Reg<MDMA_C28MDR_SPEC>

MDMA_C28SAR register accessor: an alias for Reg<MDMA_C28SAR_SPEC>

MDMA_C28TBR register accessor: an alias for Reg<MDMA_C28TBR_SPEC>

MDMA_C28TCR register accessor: an alias for Reg<MDMA_C28TCR_SPEC>

MDMA_C29BNDTR register accessor: an alias for Reg<MDMA_C29BNDTR_SPEC>

MDMA_C29BRUR register accessor: an alias for Reg<MDMA_C29BRUR_SPEC>

MDMA_C29CR register accessor: an alias for Reg<MDMA_C29CR_SPEC>

MDMA_C29DAR register accessor: an alias for Reg<MDMA_C29DAR_SPEC>

MDMA_C29ESR register accessor: an alias for Reg<MDMA_C29ESR_SPEC>

MDMA_C29IFCR register accessor: an alias for Reg<MDMA_C29IFCR_SPEC>

MDMA_C29ISR register accessor: an alias for Reg<MDMA_C29ISR_SPEC>

MDMA_C29LAR register accessor: an alias for Reg<MDMA_C29LAR_SPEC>

MDMA_C29MAR register accessor: an alias for Reg<MDMA_C29MAR_SPEC>

MDMA_C29MDR register accessor: an alias for Reg<MDMA_C29MDR_SPEC>

MDMA_C29SAR register accessor: an alias for Reg<MDMA_C29SAR_SPEC>

MDMA_C29TBR register accessor: an alias for Reg<MDMA_C29TBR_SPEC>

MDMA_C29TCR register accessor: an alias for Reg<MDMA_C29TCR_SPEC>

MDMA_C30BNDTR register accessor: an alias for Reg<MDMA_C30BNDTR_SPEC>

MDMA_C30BRUR register accessor: an alias for Reg<MDMA_C30BRUR_SPEC>

MDMA_C30CR register accessor: an alias for Reg<MDMA_C30CR_SPEC>

MDMA_C30DAR register accessor: an alias for Reg<MDMA_C30DAR_SPEC>

MDMA_C30ESR register accessor: an alias for Reg<MDMA_C30ESR_SPEC>

MDMA_C30IFCR register accessor: an alias for Reg<MDMA_C30IFCR_SPEC>

MDMA_C30ISR register accessor: an alias for Reg<MDMA_C30ISR_SPEC>

MDMA_C30LAR register accessor: an alias for Reg<MDMA_C30LAR_SPEC>

MDMA_C30MAR register accessor: an alias for Reg<MDMA_C30MAR_SPEC>

MDMA_C30MDR register accessor: an alias for Reg<MDMA_C30MDR_SPEC>

MDMA_C30SAR register accessor: an alias for Reg<MDMA_C30SAR_SPEC>

MDMA_C30TBR register accessor: an alias for Reg<MDMA_C30TBR_SPEC>

MDMA_C30TCR register accessor: an alias for Reg<MDMA_C30TCR_SPEC>

MDMA_C31BNDTR register accessor: an alias for Reg<MDMA_C31BNDTR_SPEC>

MDMA_C31BRUR register accessor: an alias for Reg<MDMA_C31BRUR_SPEC>

MDMA_C31CR register accessor: an alias for Reg<MDMA_C31CR_SPEC>

MDMA_C31DAR register accessor: an alias for Reg<MDMA_C31DAR_SPEC>

MDMA_C31ESR register accessor: an alias for Reg<MDMA_C31ESR_SPEC>

MDMA_C31IFCR register accessor: an alias for Reg<MDMA_C31IFCR_SPEC>

MDMA_C31ISR register accessor: an alias for Reg<MDMA_C31ISR_SPEC>

MDMA_C31LAR register accessor: an alias for Reg<MDMA_C31LAR_SPEC>

MDMA_C31MAR register accessor: an alias for Reg<MDMA_C31MAR_SPEC>

MDMA_C31MDR register accessor: an alias for Reg<MDMA_C31MDR_SPEC>

MDMA_C31SAR register accessor: an alias for Reg<MDMA_C31SAR_SPEC>

MDMA_C31TBR register accessor: an alias for Reg<MDMA_C31TBR_SPEC>

MDMA_C31TCR register accessor: an alias for Reg<MDMA_C31TCR_SPEC>

MDMA_GISR0 register accessor: an alias for Reg<MDMA_GISR0_SPEC>

MDMA_SGISR0 register accessor: an alias for Reg<MDMA_SGISR0_SPEC>