Module stm32mp1::stm32mp157::dma1
source · [−]Expand description
DMA1
Modules
DMA high interrupt flag clear register
DMA high interrupt status register
DMA hardware configuration 1 register
DMA hardware configuration 2register
DMA IP identification register
DMA low interrupt flag clear register
DMA low interrupt status register
This register is used to configure the concerned stream.
DMA stream 0 FIFO control register
DMA stream 0 memory 0 address register
DMA stream 0 memory 1 address register
DMA stream 0 number of data register
DMA stream 0 peripheral address register
This register is used to configure the concerned stream.
DMA stream 1 FIFO control register
DMA stream 1 memory 0 address register
DMA stream 1 memory 1 address register
DMA stream 1 number of data register
DMA stream 1 peripheral address register
This register is used to configure the concerned stream.
DMA stream 2 FIFO control register
DMA stream 2 memory 0 address register
DMA stream 2 memory 1 address register
DMA stream 2 number of data register
DMA stream 2 peripheral address register
This register is used to configure the concerned stream.
DMA stream 3 FIFO control register
DMA stream 3 memory 0 address register
DMA stream 3 memory 1 address register
DMA stream 3 number of data register
DMA stream 3 peripheral address register
This register is used to configure the concerned stream.
DMA stream 4 FIFO control register
DMA stream 4 memory 0 address register
DMA stream 4 memory 1 address register
DMA stream 4 number of data register
DMA stream 4 peripheral address register
This register is used to configure the concerned stream.
DMA stream 5 FIFO control register
DMA stream 5 memory 0 address register
DMA stream 5 memory 1 address register
DMA stream 5 number of data register
DMA stream 5 peripheral address register
This register is used to configure the concerned stream.
DMA stream 6 FIFO control register
DMA stream 6 memory 0 address register
DMA stream 6 memory 1 address register
DMA stream 6 number of data register
DMA stream 6 peripheral address register
This register is used to configure the concerned stream.
DMA stream 7 FIFO control register
DMA stream 7 memory 0 address register
DMA stream 7 memory 1 address register
DMA stream 7 number of data register
DMA stream 7 peripheral address register
DMA size identification register
This register identifies the version of the IP.
Structs
Register block
Type Definitions
DMA_HIFCR register accessor: an alias for Reg<DMA_HIFCR_SPEC>
DMA_HISR register accessor: an alias for Reg<DMA_HISR_SPEC>
DMA_HWCFGR1 register accessor: an alias for Reg<DMA_HWCFGR1_SPEC>
DMA_HWCFGR2 register accessor: an alias for Reg<DMA_HWCFGR2_SPEC>
DMA_IPDR register accessor: an alias for Reg<DMA_IPDR_SPEC>
DMA_LIFCR register accessor: an alias for Reg<DMA_LIFCR_SPEC>
DMA_LISR register accessor: an alias for Reg<DMA_LISR_SPEC>
DMA_S0CR register accessor: an alias for Reg<DMA_S0CR_SPEC>
DMA_S0FCR register accessor: an alias for Reg<DMA_S0FCR_SPEC>
DMA_S0M0AR register accessor: an alias for Reg<DMA_S0M0AR_SPEC>
DMA_S0M1AR register accessor: an alias for Reg<DMA_S0M1AR_SPEC>
DMA_S0NDTR register accessor: an alias for Reg<DMA_S0NDTR_SPEC>
DMA_S0PAR register accessor: an alias for Reg<DMA_S0PAR_SPEC>
DMA_S1CR register accessor: an alias for Reg<DMA_S1CR_SPEC>
DMA_S1FCR register accessor: an alias for Reg<DMA_S1FCR_SPEC>
DMA_S1M0AR register accessor: an alias for Reg<DMA_S1M0AR_SPEC>
DMA_S1M1AR register accessor: an alias for Reg<DMA_S1M1AR_SPEC>
DMA_S1NDTR register accessor: an alias for Reg<DMA_S1NDTR_SPEC>
DMA_S1PAR register accessor: an alias for Reg<DMA_S1PAR_SPEC>
DMA_S2CR register accessor: an alias for Reg<DMA_S2CR_SPEC>
DMA_S2FCR register accessor: an alias for Reg<DMA_S2FCR_SPEC>
DMA_S2M0AR register accessor: an alias for Reg<DMA_S2M0AR_SPEC>
DMA_S2M1AR register accessor: an alias for Reg<DMA_S2M1AR_SPEC>
DMA_S2NDTR register accessor: an alias for Reg<DMA_S2NDTR_SPEC>
DMA_S2PAR register accessor: an alias for Reg<DMA_S2PAR_SPEC>
DMA_S3CR register accessor: an alias for Reg<DMA_S3CR_SPEC>
DMA_S3FCR register accessor: an alias for Reg<DMA_S3FCR_SPEC>
DMA_S3M0AR register accessor: an alias for Reg<DMA_S3M0AR_SPEC>
DMA_S3M1AR register accessor: an alias for Reg<DMA_S3M1AR_SPEC>
DMA_S3NDTR register accessor: an alias for Reg<DMA_S3NDTR_SPEC>
DMA_S3PAR register accessor: an alias for Reg<DMA_S3PAR_SPEC>
DMA_S4CR register accessor: an alias for Reg<DMA_S4CR_SPEC>
DMA_S4FCR register accessor: an alias for Reg<DMA_S4FCR_SPEC>
DMA_S4M0AR register accessor: an alias for Reg<DMA_S4M0AR_SPEC>
DMA_S4M1AR register accessor: an alias for Reg<DMA_S4M1AR_SPEC>
DMA_S4NDTR register accessor: an alias for Reg<DMA_S4NDTR_SPEC>
DMA_S4PAR register accessor: an alias for Reg<DMA_S4PAR_SPEC>
DMA_S5CR register accessor: an alias for Reg<DMA_S5CR_SPEC>
DMA_S5FCR register accessor: an alias for Reg<DMA_S5FCR_SPEC>
DMA_S5M0AR register accessor: an alias for Reg<DMA_S5M0AR_SPEC>
DMA_S5M1AR register accessor: an alias for Reg<DMA_S5M1AR_SPEC>
DMA_S5NDTR register accessor: an alias for Reg<DMA_S5NDTR_SPEC>
DMA_S5PAR register accessor: an alias for Reg<DMA_S5PAR_SPEC>
DMA_S6CR register accessor: an alias for Reg<DMA_S6CR_SPEC>
DMA_S6FCR register accessor: an alias for Reg<DMA_S6FCR_SPEC>
DMA_S6M0AR register accessor: an alias for Reg<DMA_S6M0AR_SPEC>
DMA_S6M1AR register accessor: an alias for Reg<DMA_S6M1AR_SPEC>
DMA_S6NDTR register accessor: an alias for Reg<DMA_S6NDTR_SPEC>
DMA_S6PAR register accessor: an alias for Reg<DMA_S6PAR_SPEC>
DMA_S7CR register accessor: an alias for Reg<DMA_S7CR_SPEC>
DMA_S7FCR register accessor: an alias for Reg<DMA_S7FCR_SPEC>
DMA_S7M0AR register accessor: an alias for Reg<DMA_S7M0AR_SPEC>
DMA_S7M1AR register accessor: an alias for Reg<DMA_S7M1AR_SPEC>
DMA_S7NDTR register accessor: an alias for Reg<DMA_S7NDTR_SPEC>
DMA_S7PAR register accessor: an alias for Reg<DMA_S7PAR_SPEC>
DMA_SIDR register accessor: an alias for Reg<DMA_SIDR_SPEC>
DMA_VERR register accessor: an alias for Reg<DMA_VERR_SPEC>