stm32mp1/stm32mp157/tim15/
ccmr1_output.rs

1///Register `CCMR1_Output` reader
2pub type R = crate::R<CCMR1_OUTPUTrs>;
3///Register `CCMR1_Output` writer
4pub type W = crate::W<CCMR1_OUTPUTrs>;
5///Field `CC1S` reader - Capture/Compare 1 selection
6pub type CC1S_R = crate::FieldReader;
7///Field `CC1S` writer - Capture/Compare 1 selection
8pub type CC1S_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9///Field `OC1FE` reader - Output compare 1 fast enable
10pub type OC1FE_R = crate::BitReader;
11///Field `OC1FE` writer - Output compare 1 fast enable
12pub type OC1FE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `OC1PE` reader - Output compare 1 preload enable
14pub type OC1PE_R = crate::BitReader;
15///Field `OC1PE` writer - Output compare 1 preload enable
16pub type OC1PE_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `OC1M` reader - Output compare 1 mode
18pub type OC1M_R = crate::FieldReader;
19///Field `OC1M` writer - Output compare 1 mode
20pub type OC1M_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21///Field `OC1CE` reader - Output compare 1 clear enable
22pub type OC1CE_R = crate::BitReader;
23///Field `OC1CE` writer - Output compare 1 clear enable
24pub type OC1CE_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `CC2S` reader - Capture/Compare 2 selection
26pub type CC2S_R = crate::FieldReader;
27///Field `CC2S` writer - Capture/Compare 2 selection
28pub type CC2S_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29///Field `OC2FE` reader - Output compare 2 fast enable
30pub type OC2FE_R = crate::BitReader;
31///Field `OC2FE` writer - Output compare 2 fast enable
32pub type OC2FE_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `OC2PE` reader - Output compare 2 preload enable
34pub type OC2PE_R = crate::BitReader;
35///Field `OC2PE` writer - Output compare 2 preload enable
36pub type OC2PE_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `OC2M` reader - Output compare 2 mode
38pub type OC2M_R = crate::FieldReader;
39///Field `OC2M` writer - Output compare 2 mode
40pub type OC2M_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41///Field `OC2CE` reader - Output compare 2 clear enable
42pub type OC2CE_R = crate::BitReader;
43///Field `OC2CE` writer - Output compare 2 clear enable
44pub type OC2CE_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `OC1M_3` reader - Output Compare 1 mode - bit 3
46pub type OC1M_3_R = crate::BitReader;
47///Field `OC1M_3` writer - Output Compare 1 mode - bit 3
48pub type OC1M_3_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `OC2M_3` reader - Output Compare 2 mode - bit 3
50pub type OC2M_3_R = crate::BitReader;
51///Field `OC2M_3` writer - Output Compare 2 mode - bit 3
52pub type OC2M_3_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    ///Bits 0:1 - Capture/Compare 1 selection
55    #[inline(always)]
56    pub fn cc1s(&self) -> CC1S_R {
57        CC1S_R::new((self.bits & 3) as u8)
58    }
59    ///Bit 2 - Output compare 1 fast enable
60    #[inline(always)]
61    pub fn oc1fe(&self) -> OC1FE_R {
62        OC1FE_R::new(((self.bits >> 2) & 1) != 0)
63    }
64    ///Bit 3 - Output compare 1 preload enable
65    #[inline(always)]
66    pub fn oc1pe(&self) -> OC1PE_R {
67        OC1PE_R::new(((self.bits >> 3) & 1) != 0)
68    }
69    ///Bits 4:6 - Output compare 1 mode
70    #[inline(always)]
71    pub fn oc1m(&self) -> OC1M_R {
72        OC1M_R::new(((self.bits >> 4) & 7) as u8)
73    }
74    ///Bit 7 - Output compare 1 clear enable
75    #[inline(always)]
76    pub fn oc1ce(&self) -> OC1CE_R {
77        OC1CE_R::new(((self.bits >> 7) & 1) != 0)
78    }
79    ///Bits 8:9 - Capture/Compare 2 selection
80    #[inline(always)]
81    pub fn cc2s(&self) -> CC2S_R {
82        CC2S_R::new(((self.bits >> 8) & 3) as u8)
83    }
84    ///Bit 10 - Output compare 2 fast enable
85    #[inline(always)]
86    pub fn oc2fe(&self) -> OC2FE_R {
87        OC2FE_R::new(((self.bits >> 10) & 1) != 0)
88    }
89    ///Bit 11 - Output compare 2 preload enable
90    #[inline(always)]
91    pub fn oc2pe(&self) -> OC2PE_R {
92        OC2PE_R::new(((self.bits >> 11) & 1) != 0)
93    }
94    ///Bits 12:14 - Output compare 2 mode
95    #[inline(always)]
96    pub fn oc2m(&self) -> OC2M_R {
97        OC2M_R::new(((self.bits >> 12) & 7) as u8)
98    }
99    ///Bit 15 - Output compare 2 clear enable
100    #[inline(always)]
101    pub fn oc2ce(&self) -> OC2CE_R {
102        OC2CE_R::new(((self.bits >> 15) & 1) != 0)
103    }
104    ///Bit 16 - Output Compare 1 mode - bit 3
105    #[inline(always)]
106    pub fn oc1m_3(&self) -> OC1M_3_R {
107        OC1M_3_R::new(((self.bits >> 16) & 1) != 0)
108    }
109    ///Bit 24 - Output Compare 2 mode - bit 3
110    #[inline(always)]
111    pub fn oc2m_3(&self) -> OC2M_3_R {
112        OC2M_3_R::new(((self.bits >> 24) & 1) != 0)
113    }
114}
115impl core::fmt::Debug for R {
116    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
117        f.debug_struct("CCMR1_Output")
118            .field("oc2m_3", &self.oc2m_3())
119            .field("oc1m_3", &self.oc1m_3())
120            .field("oc2ce", &self.oc2ce())
121            .field("oc2m", &self.oc2m())
122            .field("oc2pe", &self.oc2pe())
123            .field("oc2fe", &self.oc2fe())
124            .field("cc2s", &self.cc2s())
125            .field("oc1ce", &self.oc1ce())
126            .field("oc1m", &self.oc1m())
127            .field("oc1pe", &self.oc1pe())
128            .field("oc1fe", &self.oc1fe())
129            .field("cc1s", &self.cc1s())
130            .finish()
131    }
132}
133impl W {
134    ///Bits 0:1 - Capture/Compare 1 selection
135    #[inline(always)]
136    pub fn cc1s(&mut self) -> CC1S_W<CCMR1_OUTPUTrs> {
137        CC1S_W::new(self, 0)
138    }
139    ///Bit 2 - Output compare 1 fast enable
140    #[inline(always)]
141    pub fn oc1fe(&mut self) -> OC1FE_W<CCMR1_OUTPUTrs> {
142        OC1FE_W::new(self, 2)
143    }
144    ///Bit 3 - Output compare 1 preload enable
145    #[inline(always)]
146    pub fn oc1pe(&mut self) -> OC1PE_W<CCMR1_OUTPUTrs> {
147        OC1PE_W::new(self, 3)
148    }
149    ///Bits 4:6 - Output compare 1 mode
150    #[inline(always)]
151    pub fn oc1m(&mut self) -> OC1M_W<CCMR1_OUTPUTrs> {
152        OC1M_W::new(self, 4)
153    }
154    ///Bit 7 - Output compare 1 clear enable
155    #[inline(always)]
156    pub fn oc1ce(&mut self) -> OC1CE_W<CCMR1_OUTPUTrs> {
157        OC1CE_W::new(self, 7)
158    }
159    ///Bits 8:9 - Capture/Compare 2 selection
160    #[inline(always)]
161    pub fn cc2s(&mut self) -> CC2S_W<CCMR1_OUTPUTrs> {
162        CC2S_W::new(self, 8)
163    }
164    ///Bit 10 - Output compare 2 fast enable
165    #[inline(always)]
166    pub fn oc2fe(&mut self) -> OC2FE_W<CCMR1_OUTPUTrs> {
167        OC2FE_W::new(self, 10)
168    }
169    ///Bit 11 - Output compare 2 preload enable
170    #[inline(always)]
171    pub fn oc2pe(&mut self) -> OC2PE_W<CCMR1_OUTPUTrs> {
172        OC2PE_W::new(self, 11)
173    }
174    ///Bits 12:14 - Output compare 2 mode
175    #[inline(always)]
176    pub fn oc2m(&mut self) -> OC2M_W<CCMR1_OUTPUTrs> {
177        OC2M_W::new(self, 12)
178    }
179    ///Bit 15 - Output compare 2 clear enable
180    #[inline(always)]
181    pub fn oc2ce(&mut self) -> OC2CE_W<CCMR1_OUTPUTrs> {
182        OC2CE_W::new(self, 15)
183    }
184    ///Bit 16 - Output Compare 1 mode - bit 3
185    #[inline(always)]
186    pub fn oc1m_3(&mut self) -> OC1M_3_W<CCMR1_OUTPUTrs> {
187        OC1M_3_W::new(self, 16)
188    }
189    ///Bit 24 - Output Compare 2 mode - bit 3
190    #[inline(always)]
191    pub fn oc2m_3(&mut self) -> OC2M_3_W<CCMR1_OUTPUTrs> {
192        OC2M_3_W::new(self, 24)
193    }
194}
195/**capture/compare mode register 1 (output mode)
196
197You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
198
199See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM15:CCMR1_Output)*/
200pub struct CCMR1_OUTPUTrs;
201impl crate::RegisterSpec for CCMR1_OUTPUTrs {
202    type Ux = u32;
203}
204///`read()` method returns [`ccmr1_output::R`](R) reader structure
205impl crate::Readable for CCMR1_OUTPUTrs {}
206///`write(|w| ..)` method takes [`ccmr1_output::W`](W) writer structure
207impl crate::Writable for CCMR1_OUTPUTrs {
208    type Safety = crate::Unsafe;
209}
210///`reset()` method sets CCMR1_Output to value 0
211impl crate::Resettable for CCMR1_OUTPUTrs {}
stm32mp1/stm32mp157/tim15/ccmr1_output.rs

stm32mp1/stm32mp157/tim15/
ccmr1_output.rs
