stm32mp1/stm32mp157/ddrphyc/
dx2dqstr.rs

1///Register `DX2DQSTR` reader
2pub type R = crate::R<DX2DQSTRrs>;
3///Register `DX2DQSTR` writer
4pub type W = crate::W<DX2DQSTRrs>;
5///Field `R0DGSL` reader - R0DGSL
6pub type R0DGSL_R = crate::FieldReader;
7///Field `R0DGSL` writer - R0DGSL
8pub type R0DGSL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `R0DGPS` reader - R0DGPS
10pub type R0DGPS_R = crate::FieldReader;
11///Field `R0DGPS` writer - R0DGPS
12pub type R0DGPS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13///Field `DQSDLY` reader - DQSDLY
14pub type DQSDLY_R = crate::FieldReader;
15///Field `DQSDLY` writer - DQSDLY
16pub type DQSDLY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17///Field `DQSNDLY` reader - DQSNDLY
18pub type DQSNDLY_R = crate::FieldReader;
19///Field `DQSNDLY` writer - DQSNDLY
20pub type DQSNDLY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21///Field `DMDLY` reader - DMDLY
22pub type DMDLY_R = crate::FieldReader;
23///Field `DMDLY` writer - DMDLY
24pub type DMDLY_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25impl R {
26    ///Bits 0:2 - R0DGSL
27    #[inline(always)]
28    pub fn r0dgsl(&self) -> R0DGSL_R {
29        R0DGSL_R::new((self.bits & 7) as u8)
30    }
31    ///Bits 12:13 - R0DGPS
32    #[inline(always)]
33    pub fn r0dgps(&self) -> R0DGPS_R {
34        R0DGPS_R::new(((self.bits >> 12) & 3) as u8)
35    }
36    ///Bits 20:22 - DQSDLY
37    #[inline(always)]
38    pub fn dqsdly(&self) -> DQSDLY_R {
39        DQSDLY_R::new(((self.bits >> 20) & 7) as u8)
40    }
41    ///Bits 23:25 - DQSNDLY
42    #[inline(always)]
43    pub fn dqsndly(&self) -> DQSNDLY_R {
44        DQSNDLY_R::new(((self.bits >> 23) & 7) as u8)
45    }
46    ///Bits 26:29 - DMDLY
47    #[inline(always)]
48    pub fn dmdly(&self) -> DMDLY_R {
49        DMDLY_R::new(((self.bits >> 26) & 0x0f) as u8)
50    }
51}
52impl core::fmt::Debug for R {
53    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
54        f.debug_struct("DX2DQSTR")
55            .field("r0dgsl", &self.r0dgsl())
56            .field("r0dgps", &self.r0dgps())
57            .field("dqsdly", &self.dqsdly())
58            .field("dqsndly", &self.dqsndly())
59            .field("dmdly", &self.dmdly())
60            .finish()
61    }
62}
63impl W {
64    ///Bits 0:2 - R0DGSL
65    #[inline(always)]
66    pub fn r0dgsl(&mut self) -> R0DGSL_W<DX2DQSTRrs> {
67        R0DGSL_W::new(self, 0)
68    }
69    ///Bits 12:13 - R0DGPS
70    #[inline(always)]
71    pub fn r0dgps(&mut self) -> R0DGPS_W<DX2DQSTRrs> {
72        R0DGPS_W::new(self, 12)
73    }
74    ///Bits 20:22 - DQSDLY
75    #[inline(always)]
76    pub fn dqsdly(&mut self) -> DQSDLY_W<DX2DQSTRrs> {
77        DQSDLY_W::new(self, 20)
78    }
79    ///Bits 23:25 - DQSNDLY
80    #[inline(always)]
81    pub fn dqsndly(&mut self) -> DQSNDLY_W<DX2DQSTRrs> {
82        DQSNDLY_W::new(self, 23)
83    }
84    ///Bits 26:29 - DMDLY
85    #[inline(always)]
86    pub fn dmdly(&mut self) -> DMDLY_W<DX2DQSTRrs> {
87        DMDLY_W::new(self, 26)
88    }
89}
90/**DDRPHYC byte lane 2 DQST register
91
92You can [`read`](crate::Reg::read) this register and get [`dx2dqstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dx2dqstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRPHYC:DX2DQSTR)*/
95pub struct DX2DQSTRrs;
96impl crate::RegisterSpec for DX2DQSTRrs {
97    type Ux = u32;
98}
99///`read()` method returns [`dx2dqstr::R`](R) reader structure
100impl crate::Readable for DX2DQSTRrs {}
101///`write(|w| ..)` method takes [`dx2dqstr::W`](W) writer structure
102impl crate::Writable for DX2DQSTRrs {
103    type Safety = crate::Unsafe;
104}
105///`reset()` method sets DX2DQSTR to value 0x3db0_2000
106impl crate::Resettable for DX2DQSTRrs {
107    const RESET_VALUE: u32 = 0x3db0_2000;
108}