stm32mp1/stm32mp157/ddrphyc/
dx0gcr.rs

1///Register `DX0GCR` reader
2pub type R = crate::R<DX0GCRrs>;
3///Register `DX0GCR` writer
4pub type W = crate::W<DX0GCRrs>;
5///Field `DXEN` reader - DXEN
6pub type DXEN_R = crate::BitReader;
7///Field `DXEN` writer - DXEN
8pub type DXEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DQSODT` reader - DQSODT
10pub type DQSODT_R = crate::BitReader;
11///Field `DQSODT` writer - DQSODT
12pub type DQSODT_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DQODT` reader - DQODT
14pub type DQODT_R = crate::BitReader;
15///Field `DQODT` writer - DQODT
16pub type DQODT_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `DXIOM` reader - DXIOM
18pub type DXIOM_R = crate::BitReader;
19///Field `DXIOM` writer - DXIOM
20pub type DXIOM_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `DXPDD` reader - DXPDD
22pub type DXPDD_R = crate::BitReader;
23///Field `DXPDD` writer - DXPDD
24pub type DXPDD_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `DXPDR` reader - DXPDR
26pub type DXPDR_R = crate::BitReader;
27///Field `DXPDR` writer - DXPDR
28pub type DXPDR_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `DQSRPD` reader - DQSRPD
30pub type DQSRPD_R = crate::BitReader;
31///Field `DQSRPD` writer - DQSRPD
32pub type DQSRPD_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `DSEN` reader - DSEN
34pub type DSEN_R = crate::FieldReader;
35///Field `DSEN` writer - DSEN
36pub type DSEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37///Field `DQSRTT` reader - DQSRTT
38pub type DQSRTT_R = crate::BitReader;
39///Field `DQSRTT` writer - DQSRTT
40pub type DQSRTT_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DQRTT` reader - DQRTT
42pub type DQRTT_R = crate::BitReader;
43///Field `DQRTT` writer - DQRTT
44pub type DQRTT_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `RTTOH` reader - RTTOH
46pub type RTTOH_R = crate::FieldReader;
47///Field `RTTOH` writer - RTTOH
48pub type RTTOH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
49///Field `RTTOAL` reader - RTTOAL
50pub type RTTOAL_R = crate::BitReader;
51///Field `RTTOAL` writer - RTTOAL
52pub type RTTOAL_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `R0RVSL` reader - R0RVSL
54pub type R0RVSL_R = crate::FieldReader;
55///Field `R0RVSL` writer - R0RVSL
56pub type R0RVSL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
57impl R {
58    ///Bit 0 - DXEN
59    #[inline(always)]
60    pub fn dxen(&self) -> DXEN_R {
61        DXEN_R::new((self.bits & 1) != 0)
62    }
63    ///Bit 1 - DQSODT
64    #[inline(always)]
65    pub fn dqsodt(&self) -> DQSODT_R {
66        DQSODT_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    ///Bit 2 - DQODT
69    #[inline(always)]
70    pub fn dqodt(&self) -> DQODT_R {
71        DQODT_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    ///Bit 3 - DXIOM
74    #[inline(always)]
75    pub fn dxiom(&self) -> DXIOM_R {
76        DXIOM_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    ///Bit 4 - DXPDD
79    #[inline(always)]
80    pub fn dxpdd(&self) -> DXPDD_R {
81        DXPDD_R::new(((self.bits >> 4) & 1) != 0)
82    }
83    ///Bit 5 - DXPDR
84    #[inline(always)]
85    pub fn dxpdr(&self) -> DXPDR_R {
86        DXPDR_R::new(((self.bits >> 5) & 1) != 0)
87    }
88    ///Bit 6 - DQSRPD
89    #[inline(always)]
90    pub fn dqsrpd(&self) -> DQSRPD_R {
91        DQSRPD_R::new(((self.bits >> 6) & 1) != 0)
92    }
93    ///Bits 7:8 - DSEN
94    #[inline(always)]
95    pub fn dsen(&self) -> DSEN_R {
96        DSEN_R::new(((self.bits >> 7) & 3) as u8)
97    }
98    ///Bit 9 - DQSRTT
99    #[inline(always)]
100    pub fn dqsrtt(&self) -> DQSRTT_R {
101        DQSRTT_R::new(((self.bits >> 9) & 1) != 0)
102    }
103    ///Bit 10 - DQRTT
104    #[inline(always)]
105    pub fn dqrtt(&self) -> DQRTT_R {
106        DQRTT_R::new(((self.bits >> 10) & 1) != 0)
107    }
108    ///Bits 11:12 - RTTOH
109    #[inline(always)]
110    pub fn rttoh(&self) -> RTTOH_R {
111        RTTOH_R::new(((self.bits >> 11) & 3) as u8)
112    }
113    ///Bit 13 - RTTOAL
114    #[inline(always)]
115    pub fn rttoal(&self) -> RTTOAL_R {
116        RTTOAL_R::new(((self.bits >> 13) & 1) != 0)
117    }
118    ///Bits 14:16 - R0RVSL
119    #[inline(always)]
120    pub fn r0rvsl(&self) -> R0RVSL_R {
121        R0RVSL_R::new(((self.bits >> 14) & 7) as u8)
122    }
123}
124impl core::fmt::Debug for R {
125    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
126        f.debug_struct("DX0GCR")
127            .field("dxen", &self.dxen())
128            .field("dqsodt", &self.dqsodt())
129            .field("dqodt", &self.dqodt())
130            .field("dxiom", &self.dxiom())
131            .field("dxpdd", &self.dxpdd())
132            .field("dxpdr", &self.dxpdr())
133            .field("dqsrpd", &self.dqsrpd())
134            .field("dsen", &self.dsen())
135            .field("dqsrtt", &self.dqsrtt())
136            .field("dqrtt", &self.dqrtt())
137            .field("rttoh", &self.rttoh())
138            .field("rttoal", &self.rttoal())
139            .field("r0rvsl", &self.r0rvsl())
140            .finish()
141    }
142}
143impl W {
144    ///Bit 0 - DXEN
145    #[inline(always)]
146    pub fn dxen(&mut self) -> DXEN_W<DX0GCRrs> {
147        DXEN_W::new(self, 0)
148    }
149    ///Bit 1 - DQSODT
150    #[inline(always)]
151    pub fn dqsodt(&mut self) -> DQSODT_W<DX0GCRrs> {
152        DQSODT_W::new(self, 1)
153    }
154    ///Bit 2 - DQODT
155    #[inline(always)]
156    pub fn dqodt(&mut self) -> DQODT_W<DX0GCRrs> {
157        DQODT_W::new(self, 2)
158    }
159    ///Bit 3 - DXIOM
160    #[inline(always)]
161    pub fn dxiom(&mut self) -> DXIOM_W<DX0GCRrs> {
162        DXIOM_W::new(self, 3)
163    }
164    ///Bit 4 - DXPDD
165    #[inline(always)]
166    pub fn dxpdd(&mut self) -> DXPDD_W<DX0GCRrs> {
167        DXPDD_W::new(self, 4)
168    }
169    ///Bit 5 - DXPDR
170    #[inline(always)]
171    pub fn dxpdr(&mut self) -> DXPDR_W<DX0GCRrs> {
172        DXPDR_W::new(self, 5)
173    }
174    ///Bit 6 - DQSRPD
175    #[inline(always)]
176    pub fn dqsrpd(&mut self) -> DQSRPD_W<DX0GCRrs> {
177        DQSRPD_W::new(self, 6)
178    }
179    ///Bits 7:8 - DSEN
180    #[inline(always)]
181    pub fn dsen(&mut self) -> DSEN_W<DX0GCRrs> {
182        DSEN_W::new(self, 7)
183    }
184    ///Bit 9 - DQSRTT
185    #[inline(always)]
186    pub fn dqsrtt(&mut self) -> DQSRTT_W<DX0GCRrs> {
187        DQSRTT_W::new(self, 9)
188    }
189    ///Bit 10 - DQRTT
190    #[inline(always)]
191    pub fn dqrtt(&mut self) -> DQRTT_W<DX0GCRrs> {
192        DQRTT_W::new(self, 10)
193    }
194    ///Bits 11:12 - RTTOH
195    #[inline(always)]
196    pub fn rttoh(&mut self) -> RTTOH_W<DX0GCRrs> {
197        RTTOH_W::new(self, 11)
198    }
199    ///Bit 13 - RTTOAL
200    #[inline(always)]
201    pub fn rttoal(&mut self) -> RTTOAL_W<DX0GCRrs> {
202        RTTOAL_W::new(self, 13)
203    }
204    ///Bits 14:16 - R0RVSL
205    #[inline(always)]
206    pub fn r0rvsl(&mut self) -> R0RVSL_W<DX0GCRrs> {
207        R0RVSL_W::new(self, 14)
208    }
209}
210/**DDRPHYC byte lane 0 GC register
211
212You can [`read`](crate::Reg::read) this register and get [`dx0gcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dx0gcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRPHYC:DX0GCR)*/
215pub struct DX0GCRrs;
216impl crate::RegisterSpec for DX0GCRrs {
217    type Ux = u32;
218}
219///`read()` method returns [`dx0gcr::R`](R) reader structure
220impl crate::Readable for DX0GCRrs {}
221///`write(|w| ..)` method takes [`dx0gcr::W`](W) writer structure
222impl crate::Writable for DX0GCRrs {
223    type Safety = crate::Unsafe;
224}
225///`reset()` method sets DX0GCR to value 0xee81
226impl crate::Resettable for DX0GCRrs {
227    const RESET_VALUE: u32 = 0xee81;
228}
stm32mp1/stm32mp157/ddrphyc/dx0gcr.rs

stm32mp1/stm32mp157/ddrphyc/
dx0gcr.rs
