stm32mp1/stm32mp157/ddrphyc/
ddr3_mr2.rs

1///Register `DDR3_MR2` reader
2pub type R = crate::R<DDR3_MR2rs>;
3///Register `DDR3_MR2` writer
4pub type W = crate::W<DDR3_MR2rs>;
5///Field `PASR` reader - PASR
6pub type PASR_R = crate::FieldReader;
7///Field `PASR` writer - PASR
8pub type PASR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `CWL` reader - CWL
10pub type CWL_R = crate::FieldReader;
11///Field `CWL` writer - CWL
12pub type CWL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13///Field `ASR` reader - ASR
14pub type ASR_R = crate::BitReader;
15///Field `ASR` writer - ASR
16pub type ASR_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `SRT` reader - SRT
18pub type SRT_R = crate::BitReader;
19///Field `SRT` writer - SRT
20pub type SRT_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `RTTWR` reader - RTTWR
22pub type RTTWR_R = crate::FieldReader;
23///Field `RTTWR` writer - RTTWR
24pub type RTTWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26    ///Bits 0:2 - PASR
27    #[inline(always)]
28    pub fn pasr(&self) -> PASR_R {
29        PASR_R::new((self.bits & 7) as u8)
30    }
31    ///Bits 3:5 - CWL
32    #[inline(always)]
33    pub fn cwl(&self) -> CWL_R {
34        CWL_R::new(((self.bits >> 3) & 7) as u8)
35    }
36    ///Bit 6 - ASR
37    #[inline(always)]
38    pub fn asr(&self) -> ASR_R {
39        ASR_R::new(((self.bits >> 6) & 1) != 0)
40    }
41    ///Bit 7 - SRT
42    #[inline(always)]
43    pub fn srt(&self) -> SRT_R {
44        SRT_R::new(((self.bits >> 7) & 1) != 0)
45    }
46    ///Bits 9:10 - RTTWR
47    #[inline(always)]
48    pub fn rttwr(&self) -> RTTWR_R {
49        RTTWR_R::new(((self.bits >> 9) & 3) as u8)
50    }
51}
52impl core::fmt::Debug for R {
53    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
54        f.debug_struct("DDR3_MR2")
55            .field("pasr", &self.pasr())
56            .field("cwl", &self.cwl())
57            .field("asr", &self.asr())
58            .field("srt", &self.srt())
59            .field("rttwr", &self.rttwr())
60            .finish()
61    }
62}
63impl W {
64    ///Bits 0:2 - PASR
65    #[inline(always)]
66    pub fn pasr(&mut self) -> PASR_W<DDR3_MR2rs> {
67        PASR_W::new(self, 0)
68    }
69    ///Bits 3:5 - CWL
70    #[inline(always)]
71    pub fn cwl(&mut self) -> CWL_W<DDR3_MR2rs> {
72        CWL_W::new(self, 3)
73    }
74    ///Bit 6 - ASR
75    #[inline(always)]
76    pub fn asr(&mut self) -> ASR_W<DDR3_MR2rs> {
77        ASR_W::new(self, 6)
78    }
79    ///Bit 7 - SRT
80    #[inline(always)]
81    pub fn srt(&mut self) -> SRT_W<DDR3_MR2rs> {
82        SRT_W::new(self, 7)
83    }
84    ///Bits 9:10 - RTTWR
85    #[inline(always)]
86    pub fn rttwr(&mut self) -> RTTWR_W<DDR3_MR2rs> {
87        RTTWR_W::new(self, 9)
88    }
89}
90/**DDRPHYC MR2 register for DDR3
91
92You can [`read`](crate::Reg::read) this register and get [`ddr3_mr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddr3_mr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRPHYC:DDR3_MR2)*/
95pub struct DDR3_MR2rs;
96impl crate::RegisterSpec for DDR3_MR2rs {
97    type Ux = u16;
98}
99///`read()` method returns [`ddr3_mr2::R`](R) reader structure
100impl crate::Readable for DDR3_MR2rs {}
101///`write(|w| ..)` method takes [`ddr3_mr2::W`](W) writer structure
102impl crate::Writable for DDR3_MR2rs {
103    type Safety = crate::Unsafe;
104}
105///`reset()` method sets DDR3_MR2 to value 0
106impl crate::Resettable for DDR3_MR2rs {}
stm32mp1/stm32mp157/ddrphyc/ddr3_mr2.rs

stm32mp1/stm32mp157/ddrphyc/
ddr3_mr2.rs
