stm32mp1/stm32mp157/ddrphyc/
ddr3_mr1.rs

1///Register `DDR3_MR1` reader
2pub type R = crate::R<DDR3_MR1rs>;
3///Register `DDR3_MR1` writer
4pub type W = crate::W<DDR3_MR1rs>;
5///Field `DE` reader - DE
6pub type DE_R = crate::BitReader;
7///Field `DE` writer - DE
8pub type DE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DIC0` reader - DIC0
10pub type DIC0_R = crate::BitReader;
11///Field `DIC0` writer - DIC0
12pub type DIC0_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `RTT0` reader - RTT0
14pub type RTT0_R = crate::BitReader;
15///Field `RTT0` writer - RTT0
16pub type RTT0_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `AL` reader - AL
18pub type AL_R = crate::FieldReader;
19///Field `AL` writer - AL
20pub type AL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21///Field `DIC1` reader - DIC1
22pub type DIC1_R = crate::BitReader;
23///Field `DIC1` writer - DIC1
24pub type DIC1_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `RTT1` reader - RTT1
26pub type RTT1_R = crate::BitReader;
27///Field `RTT1` writer - RTT1
28pub type RTT1_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `LEVEL` reader - LEVEL
30pub type LEVEL_R = crate::BitReader;
31///Field `LEVEL` writer - LEVEL
32pub type LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `RTT2` reader - RTT2
34pub type RTT2_R = crate::BitReader;
35///Field `RTT2` writer - RTT2
36pub type RTT2_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `TDQS` reader - TDQS
38pub type TDQS_R = crate::BitReader;
39///Field `TDQS` writer - TDQS
40pub type TDQS_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `QOFF` reader - QOFF
42pub type QOFF_R = crate::BitReader;
43///Field `QOFF` writer - QOFF
44pub type QOFF_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    ///Bit 0 - DE
47    #[inline(always)]
48    pub fn de(&self) -> DE_R {
49        DE_R::new((self.bits & 1) != 0)
50    }
51    ///Bit 1 - DIC0
52    #[inline(always)]
53    pub fn dic0(&self) -> DIC0_R {
54        DIC0_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    ///Bit 2 - RTT0
57    #[inline(always)]
58    pub fn rtt0(&self) -> RTT0_R {
59        RTT0_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    ///Bits 3:4 - AL
62    #[inline(always)]
63    pub fn al(&self) -> AL_R {
64        AL_R::new(((self.bits >> 3) & 3) as u8)
65    }
66    ///Bit 5 - DIC1
67    #[inline(always)]
68    pub fn dic1(&self) -> DIC1_R {
69        DIC1_R::new(((self.bits >> 5) & 1) != 0)
70    }
71    ///Bit 6 - RTT1
72    #[inline(always)]
73    pub fn rtt1(&self) -> RTT1_R {
74        RTT1_R::new(((self.bits >> 6) & 1) != 0)
75    }
76    ///Bit 7 - LEVEL
77    #[inline(always)]
78    pub fn level(&self) -> LEVEL_R {
79        LEVEL_R::new(((self.bits >> 7) & 1) != 0)
80    }
81    ///Bit 9 - RTT2
82    #[inline(always)]
83    pub fn rtt2(&self) -> RTT2_R {
84        RTT2_R::new(((self.bits >> 9) & 1) != 0)
85    }
86    ///Bit 11 - TDQS
87    #[inline(always)]
88    pub fn tdqs(&self) -> TDQS_R {
89        TDQS_R::new(((self.bits >> 11) & 1) != 0)
90    }
91    ///Bit 12 - QOFF
92    #[inline(always)]
93    pub fn qoff(&self) -> QOFF_R {
94        QOFF_R::new(((self.bits >> 12) & 1) != 0)
95    }
96}
97impl core::fmt::Debug for R {
98    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99        f.debug_struct("DDR3_MR1")
100            .field("de", &self.de())
101            .field("dic0", &self.dic0())
102            .field("rtt0", &self.rtt0())
103            .field("al", &self.al())
104            .field("dic1", &self.dic1())
105            .field("rtt1", &self.rtt1())
106            .field("level", &self.level())
107            .field("rtt2", &self.rtt2())
108            .field("tdqs", &self.tdqs())
109            .field("qoff", &self.qoff())
110            .finish()
111    }
112}
113impl W {
114    ///Bit 0 - DE
115    #[inline(always)]
116    pub fn de(&mut self) -> DE_W<DDR3_MR1rs> {
117        DE_W::new(self, 0)
118    }
119    ///Bit 1 - DIC0
120    #[inline(always)]
121    pub fn dic0(&mut self) -> DIC0_W<DDR3_MR1rs> {
122        DIC0_W::new(self, 1)
123    }
124    ///Bit 2 - RTT0
125    #[inline(always)]
126    pub fn rtt0(&mut self) -> RTT0_W<DDR3_MR1rs> {
127        RTT0_W::new(self, 2)
128    }
129    ///Bits 3:4 - AL
130    #[inline(always)]
131    pub fn al(&mut self) -> AL_W<DDR3_MR1rs> {
132        AL_W::new(self, 3)
133    }
134    ///Bit 5 - DIC1
135    #[inline(always)]
136    pub fn dic1(&mut self) -> DIC1_W<DDR3_MR1rs> {
137        DIC1_W::new(self, 5)
138    }
139    ///Bit 6 - RTT1
140    #[inline(always)]
141    pub fn rtt1(&mut self) -> RTT1_W<DDR3_MR1rs> {
142        RTT1_W::new(self, 6)
143    }
144    ///Bit 7 - LEVEL
145    #[inline(always)]
146    pub fn level(&mut self) -> LEVEL_W<DDR3_MR1rs> {
147        LEVEL_W::new(self, 7)
148    }
149    ///Bit 9 - RTT2
150    #[inline(always)]
151    pub fn rtt2(&mut self) -> RTT2_W<DDR3_MR1rs> {
152        RTT2_W::new(self, 9)
153    }
154    ///Bit 11 - TDQS
155    #[inline(always)]
156    pub fn tdqs(&mut self) -> TDQS_W<DDR3_MR1rs> {
157        TDQS_W::new(self, 11)
158    }
159    ///Bit 12 - QOFF
160    #[inline(always)]
161    pub fn qoff(&mut self) -> QOFF_W<DDR3_MR1rs> {
162        QOFF_W::new(self, 12)
163    }
164}
165/**DDRPHYC MR1 register for DDR3
166
167You can [`read`](crate::Reg::read) this register and get [`ddr3_mr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddr3_mr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRPHYC:DDR3_MR1)*/
170pub struct DDR3_MR1rs;
171impl crate::RegisterSpec for DDR3_MR1rs {
172    type Ux = u16;
173}
174///`read()` method returns [`ddr3_mr1::R`](R) reader structure
175impl crate::Readable for DDR3_MR1rs {}
176///`write(|w| ..)` method takes [`ddr3_mr1::W`](W) writer structure
177impl crate::Writable for DDR3_MR1rs {
178    type Safety = crate::Unsafe;
179}
180///`reset()` method sets DDR3_MR1 to value 0
181impl crate::Resettable for DDR3_MR1rs {}
stm32mp1/stm32mp157/ddrphyc/ddr3_mr1.rs

stm32mp1/stm32mp157/ddrphyc/
ddr3_mr1.rs
