stm32mp1/stm32mp157/ddrctrl/
sched1.rs

1///Register `SCHED1` reader
2pub type R = crate::R<SCHED1rs>;
3///Register `SCHED1` writer
4pub type W = crate::W<SCHED1rs>;
5///Field `PAGECLOSE_TIMER` reader - PAGECLOSE_TIMER
6pub type PAGECLOSE_TIMER_R = crate::FieldReader;
7///Field `PAGECLOSE_TIMER` writer - PAGECLOSE_TIMER
8pub type PAGECLOSE_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9impl R {
10    ///Bits 0:7 - PAGECLOSE_TIMER
11    #[inline(always)]
12    pub fn pageclose_timer(&self) -> PAGECLOSE_TIMER_R {
13        PAGECLOSE_TIMER_R::new((self.bits & 0xff) as u8)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("SCHED1")
19            .field("pageclose_timer", &self.pageclose_timer())
20            .finish()
21    }
22}
23impl W {
24    ///Bits 0:7 - PAGECLOSE_TIMER
25    #[inline(always)]
26    pub fn pageclose_timer(&mut self) -> PAGECLOSE_TIMER_W<SCHED1rs> {
27        PAGECLOSE_TIMER_W::new(self, 0)
28    }
29}
30/**DDRCTRL scheduler control register 1
31
32You can [`read`](crate::Reg::read) this register and get [`sched1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sched1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
33
34See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRCTRL:SCHED1)*/
35pub struct SCHED1rs;
36impl crate::RegisterSpec for SCHED1rs {
37    type Ux = u32;
38}
39///`read()` method returns [`sched1::R`](R) reader structure
40impl crate::Readable for SCHED1rs {}
41///`write(|w| ..)` method takes [`sched1::W`](W) writer structure
42impl crate::Writable for SCHED1rs {
43    type Safety = crate::Unsafe;
44}
45///`reset()` method sets SCHED1 to value 0
46impl crate::Resettable for SCHED1rs {}
stm32mp1/stm32mp157/ddrctrl/sched1.rs

stm32mp1/stm32mp157/ddrctrl/
sched1.rs
