stm32mp1/stm32mp157/ddrctrl/
sched.rs

1///Register `SCHED` reader
2pub type R = crate::R<SCHEDrs>;
3///Register `SCHED` writer
4pub type W = crate::W<SCHEDrs>;
5///Field `FORCE_LOW_PRI_N` reader - FORCE_LOW_PRI_N
6pub type FORCE_LOW_PRI_N_R = crate::BitReader;
7///Field `FORCE_LOW_PRI_N` writer - FORCE_LOW_PRI_N
8pub type FORCE_LOW_PRI_N_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `PREFER_WRITE` reader - PREFER_WRITE
10pub type PREFER_WRITE_R = crate::BitReader;
11///Field `PREFER_WRITE` writer - PREFER_WRITE
12pub type PREFER_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `PAGECLOSE` reader - PAGECLOSE
14pub type PAGECLOSE_R = crate::BitReader;
15///Field `PAGECLOSE` writer - PAGECLOSE
16pub type PAGECLOSE_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `LPR_NUM_ENTRIES` reader - LPR_NUM_ENTRIES
18pub type LPR_NUM_ENTRIES_R = crate::FieldReader;
19///Field `LPR_NUM_ENTRIES` writer - LPR_NUM_ENTRIES
20pub type LPR_NUM_ENTRIES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21///Field `GO2CRITICAL_HYSTERESIS` reader - GO2CRITICAL_HYSTERESIS
22pub type GO2CRITICAL_HYSTERESIS_R = crate::FieldReader;
23///Field `GO2CRITICAL_HYSTERESIS` writer - GO2CRITICAL_HYSTERESIS
24pub type GO2CRITICAL_HYSTERESIS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25///Field `RDWR_IDLE_GAP` reader - RDWR_IDLE_GAP
26pub type RDWR_IDLE_GAP_R = crate::FieldReader;
27///Field `RDWR_IDLE_GAP` writer - RDWR_IDLE_GAP
28pub type RDWR_IDLE_GAP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
29impl R {
30    ///Bit 0 - FORCE_LOW_PRI_N
31    #[inline(always)]
32    pub fn force_low_pri_n(&self) -> FORCE_LOW_PRI_N_R {
33        FORCE_LOW_PRI_N_R::new((self.bits & 1) != 0)
34    }
35    ///Bit 1 - PREFER_WRITE
36    #[inline(always)]
37    pub fn prefer_write(&self) -> PREFER_WRITE_R {
38        PREFER_WRITE_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    ///Bit 2 - PAGECLOSE
41    #[inline(always)]
42    pub fn pageclose(&self) -> PAGECLOSE_R {
43        PAGECLOSE_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    ///Bits 8:11 - LPR_NUM_ENTRIES
46    #[inline(always)]
47    pub fn lpr_num_entries(&self) -> LPR_NUM_ENTRIES_R {
48        LPR_NUM_ENTRIES_R::new(((self.bits >> 8) & 0x0f) as u8)
49    }
50    ///Bits 16:23 - GO2CRITICAL_HYSTERESIS
51    #[inline(always)]
52    pub fn go2critical_hysteresis(&self) -> GO2CRITICAL_HYSTERESIS_R {
53        GO2CRITICAL_HYSTERESIS_R::new(((self.bits >> 16) & 0xff) as u8)
54    }
55    ///Bits 24:30 - RDWR_IDLE_GAP
56    #[inline(always)]
57    pub fn rdwr_idle_gap(&self) -> RDWR_IDLE_GAP_R {
58        RDWR_IDLE_GAP_R::new(((self.bits >> 24) & 0x7f) as u8)
59    }
60}
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("SCHED")
64            .field("force_low_pri_n", &self.force_low_pri_n())
65            .field("prefer_write", &self.prefer_write())
66            .field("pageclose", &self.pageclose())
67            .field("lpr_num_entries", &self.lpr_num_entries())
68            .field("go2critical_hysteresis", &self.go2critical_hysteresis())
69            .field("rdwr_idle_gap", &self.rdwr_idle_gap())
70            .finish()
71    }
72}
73impl W {
74    ///Bit 0 - FORCE_LOW_PRI_N
75    #[inline(always)]
76    pub fn force_low_pri_n(&mut self) -> FORCE_LOW_PRI_N_W<SCHEDrs> {
77        FORCE_LOW_PRI_N_W::new(self, 0)
78    }
79    ///Bit 1 - PREFER_WRITE
80    #[inline(always)]
81    pub fn prefer_write(&mut self) -> PREFER_WRITE_W<SCHEDrs> {
82        PREFER_WRITE_W::new(self, 1)
83    }
84    ///Bit 2 - PAGECLOSE
85    #[inline(always)]
86    pub fn pageclose(&mut self) -> PAGECLOSE_W<SCHEDrs> {
87        PAGECLOSE_W::new(self, 2)
88    }
89    ///Bits 8:11 - LPR_NUM_ENTRIES
90    #[inline(always)]
91    pub fn lpr_num_entries(&mut self) -> LPR_NUM_ENTRIES_W<SCHEDrs> {
92        LPR_NUM_ENTRIES_W::new(self, 8)
93    }
94    ///Bits 16:23 - GO2CRITICAL_HYSTERESIS
95    #[inline(always)]
96    pub fn go2critical_hysteresis(&mut self) -> GO2CRITICAL_HYSTERESIS_W<SCHEDrs> {
97        GO2CRITICAL_HYSTERESIS_W::new(self, 16)
98    }
99    ///Bits 24:30 - RDWR_IDLE_GAP
100    #[inline(always)]
101    pub fn rdwr_idle_gap(&mut self) -> RDWR_IDLE_GAP_W<SCHEDrs> {
102        RDWR_IDLE_GAP_W::new(self, 24)
103    }
104}
105/**DDRCTRL scheduler control register
106
107You can [`read`](crate::Reg::read) this register and get [`sched::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sched::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108
109See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRCTRL:SCHED)*/
110pub struct SCHEDrs;
111impl crate::RegisterSpec for SCHEDrs {
112    type Ux = u32;
113}
114///`read()` method returns [`sched::R`](R) reader structure
115impl crate::Readable for SCHEDrs {}
116///`write(|w| ..)` method takes [`sched::W`](W) writer structure
117impl crate::Writable for SCHEDrs {
118    type Safety = crate::Unsafe;
119}
120///`reset()` method sets SCHED to value 0x0805
121impl crate::Resettable for SCHEDrs {
122    const RESET_VALUE: u32 = 0x0805;
123}
stm32mp1/stm32mp157/ddrctrl/sched.rs

stm32mp1/stm32mp157/ddrctrl/
sched.rs
