stm32mp1/stm32mp157/ddrctrl/
pwrctl.rs

1///Register `PWRCTL` reader
2pub type R = crate::R<PWRCTLrs>;
3///Register `PWRCTL` writer
4pub type W = crate::W<PWRCTLrs>;
5///Field `SELFREF_EN` reader - SELFREF_EN
6pub type SELFREF_EN_R = crate::BitReader;
7///Field `SELFREF_EN` writer - SELFREF_EN
8pub type SELFREF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `POWERDOWN_EN` reader - POWERDOWN_EN
10pub type POWERDOWN_EN_R = crate::BitReader;
11///Field `POWERDOWN_EN` writer - POWERDOWN_EN
12pub type POWERDOWN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DEEPPOWERDOWN_EN` reader - DEEPPOWERDOWN_EN
14pub type DEEPPOWERDOWN_EN_R = crate::BitReader;
15///Field `DEEPPOWERDOWN_EN` writer - DEEPPOWERDOWN_EN
16pub type DEEPPOWERDOWN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `EN_DFI_DRAM_CLK_DISABLE` reader - EN_DFI_DRAM_CLK_DISABLE
18pub type EN_DFI_DRAM_CLK_DISABLE_R = crate::BitReader;
19///Field `EN_DFI_DRAM_CLK_DISABLE` writer - EN_DFI_DRAM_CLK_DISABLE
20pub type EN_DFI_DRAM_CLK_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `SELFREF_SW` reader - SELFREF_SW
22pub type SELFREF_SW_R = crate::BitReader;
23///Field `SELFREF_SW` writer - SELFREF_SW
24pub type SELFREF_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `DIS_CAM_DRAIN_SELFREF` reader - DIS_CAM_DRAIN_SELFREF
26pub type DIS_CAM_DRAIN_SELFREF_R = crate::BitReader;
27///Field `DIS_CAM_DRAIN_SELFREF` writer - DIS_CAM_DRAIN_SELFREF
28pub type DIS_CAM_DRAIN_SELFREF_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    ///Bit 0 - SELFREF_EN
31    #[inline(always)]
32    pub fn selfref_en(&self) -> SELFREF_EN_R {
33        SELFREF_EN_R::new((self.bits & 1) != 0)
34    }
35    ///Bit 1 - POWERDOWN_EN
36    #[inline(always)]
37    pub fn powerdown_en(&self) -> POWERDOWN_EN_R {
38        POWERDOWN_EN_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    ///Bit 2 - DEEPPOWERDOWN_EN
41    #[inline(always)]
42    pub fn deeppowerdown_en(&self) -> DEEPPOWERDOWN_EN_R {
43        DEEPPOWERDOWN_EN_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    ///Bit 3 - EN_DFI_DRAM_CLK_DISABLE
46    #[inline(always)]
47    pub fn en_dfi_dram_clk_disable(&self) -> EN_DFI_DRAM_CLK_DISABLE_R {
48        EN_DFI_DRAM_CLK_DISABLE_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    ///Bit 5 - SELFREF_SW
51    #[inline(always)]
52    pub fn selfref_sw(&self) -> SELFREF_SW_R {
53        SELFREF_SW_R::new(((self.bits >> 5) & 1) != 0)
54    }
55    ///Bit 7 - DIS_CAM_DRAIN_SELFREF
56    #[inline(always)]
57    pub fn dis_cam_drain_selfref(&self) -> DIS_CAM_DRAIN_SELFREF_R {
58        DIS_CAM_DRAIN_SELFREF_R::new(((self.bits >> 7) & 1) != 0)
59    }
60}
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("PWRCTL")
64            .field("selfref_en", &self.selfref_en())
65            .field("powerdown_en", &self.powerdown_en())
66            .field("deeppowerdown_en", &self.deeppowerdown_en())
67            .field("en_dfi_dram_clk_disable", &self.en_dfi_dram_clk_disable())
68            .field("selfref_sw", &self.selfref_sw())
69            .field("dis_cam_drain_selfref", &self.dis_cam_drain_selfref())
70            .finish()
71    }
72}
73impl W {
74    ///Bit 0 - SELFREF_EN
75    #[inline(always)]
76    pub fn selfref_en(&mut self) -> SELFREF_EN_W<PWRCTLrs> {
77        SELFREF_EN_W::new(self, 0)
78    }
79    ///Bit 1 - POWERDOWN_EN
80    #[inline(always)]
81    pub fn powerdown_en(&mut self) -> POWERDOWN_EN_W<PWRCTLrs> {
82        POWERDOWN_EN_W::new(self, 1)
83    }
84    ///Bit 2 - DEEPPOWERDOWN_EN
85    #[inline(always)]
86    pub fn deeppowerdown_en(&mut self) -> DEEPPOWERDOWN_EN_W<PWRCTLrs> {
87        DEEPPOWERDOWN_EN_W::new(self, 2)
88    }
89    ///Bit 3 - EN_DFI_DRAM_CLK_DISABLE
90    #[inline(always)]
91    pub fn en_dfi_dram_clk_disable(&mut self) -> EN_DFI_DRAM_CLK_DISABLE_W<PWRCTLrs> {
92        EN_DFI_DRAM_CLK_DISABLE_W::new(self, 3)
93    }
94    ///Bit 5 - SELFREF_SW
95    #[inline(always)]
96    pub fn selfref_sw(&mut self) -> SELFREF_SW_W<PWRCTLrs> {
97        SELFREF_SW_W::new(self, 5)
98    }
99    ///Bit 7 - DIS_CAM_DRAIN_SELFREF
100    #[inline(always)]
101    pub fn dis_cam_drain_selfref(&mut self) -> DIS_CAM_DRAIN_SELFREF_W<PWRCTLrs> {
102        DIS_CAM_DRAIN_SELFREF_W::new(self, 7)
103    }
104}
105/**DDRCTRL low power control register
106
107You can [`read`](crate::Reg::read) this register and get [`pwrctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108
109See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRCTRL:PWRCTL)*/
110pub struct PWRCTLrs;
111impl crate::RegisterSpec for PWRCTLrs {
112    type Ux = u32;
113}
114///`read()` method returns [`pwrctl::R`](R) reader structure
115impl crate::Readable for PWRCTLrs {}
116///`write(|w| ..)` method takes [`pwrctl::W`](W) writer structure
117impl crate::Writable for PWRCTLrs {
118    type Safety = crate::Unsafe;
119}
120///`reset()` method sets PWRCTL to value 0
121impl crate::Resettable for PWRCTLrs {}
stm32mp1/stm32mp157/ddrctrl/pwrctl.rs

stm32mp1/stm32mp157/ddrctrl/
pwrctl.rs
