stm32mp1/stm32mp157/ddrctrl/
init2.rs

1///Register `INIT2` reader
2pub type R = crate::R<INIT2rs>;
3///Register `INIT2` writer
4pub type W = crate::W<INIT2rs>;
5///Field `MIN_STABLE_CLOCK_X1` reader - MIN_STABLE_CLOCK_X1
6pub type MIN_STABLE_CLOCK_X1_R = crate::FieldReader;
7///Field `MIN_STABLE_CLOCK_X1` writer - MIN_STABLE_CLOCK_X1
8pub type MIN_STABLE_CLOCK_X1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `IDLE_AFTER_RESET_X32` reader - IDLE_AFTER_RESET_X32
10pub type IDLE_AFTER_RESET_X32_R = crate::FieldReader;
11///Field `IDLE_AFTER_RESET_X32` writer - IDLE_AFTER_RESET_X32
12pub type IDLE_AFTER_RESET_X32_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13impl R {
14    ///Bits 0:3 - MIN_STABLE_CLOCK_X1
15    #[inline(always)]
16    pub fn min_stable_clock_x1(&self) -> MIN_STABLE_CLOCK_X1_R {
17        MIN_STABLE_CLOCK_X1_R::new((self.bits & 0x0f) as u8)
18    }
19    ///Bits 8:15 - IDLE_AFTER_RESET_X32
20    #[inline(always)]
21    pub fn idle_after_reset_x32(&self) -> IDLE_AFTER_RESET_X32_R {
22        IDLE_AFTER_RESET_X32_R::new(((self.bits >> 8) & 0xff) as u8)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("INIT2")
28            .field("min_stable_clock_x1", &self.min_stable_clock_x1())
29            .field("idle_after_reset_x32", &self.idle_after_reset_x32())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 0:3 - MIN_STABLE_CLOCK_X1
35    #[inline(always)]
36    pub fn min_stable_clock_x1(&mut self) -> MIN_STABLE_CLOCK_X1_W<INIT2rs> {
37        MIN_STABLE_CLOCK_X1_W::new(self, 0)
38    }
39    ///Bits 8:15 - IDLE_AFTER_RESET_X32
40    #[inline(always)]
41    pub fn idle_after_reset_x32(&mut self) -> IDLE_AFTER_RESET_X32_W<INIT2rs> {
42        IDLE_AFTER_RESET_X32_W::new(self, 8)
43    }
44}
45/**DDRCTRL SDRAM initialization register 2
46
47You can [`read`](crate::Reg::read) this register and get [`init2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`init2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRCTRL:INIT2)*/
50pub struct INIT2rs;
51impl crate::RegisterSpec for INIT2rs {
52    type Ux = u32;
53}
54///`read()` method returns [`init2::R`](R) reader structure
55impl crate::Readable for INIT2rs {}
56///`write(|w| ..)` method takes [`init2::W`](W) writer structure
57impl crate::Writable for INIT2rs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets INIT2 to value 0x0d05
61impl crate::Resettable for INIT2rs {
62    const RESET_VALUE: u32 = 0x0d05;
63}
stm32mp1/stm32mp157/ddrctrl/init2.rs

stm32mp1/stm32mp157/ddrctrl/
init2.rs
