stm32mp1/stm32mp157/ddrctrl/
init0.rs

1///Register `INIT0` reader
2pub type R = crate::R<INIT0rs>;
3///Register `INIT0` writer
4pub type W = crate::W<INIT0rs>;
5///Field `PRE_CKE_X1024` reader - PRE_CKE_X1024
6pub type PRE_CKE_X1024_R = crate::FieldReader<u16>;
7///Field `PRE_CKE_X1024` writer - PRE_CKE_X1024
8pub type PRE_CKE_X1024_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9///Field `POST_CKE_X1024` reader - POST_CKE_X1024
10pub type POST_CKE_X1024_R = crate::FieldReader<u16>;
11///Field `POST_CKE_X1024` writer - POST_CKE_X1024
12pub type POST_CKE_X1024_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
13///Field `SKIP_DRAM_INIT` reader - SKIP_DRAM_INIT
14pub type SKIP_DRAM_INIT_R = crate::FieldReader;
15///Field `SKIP_DRAM_INIT` writer - SKIP_DRAM_INIT
16pub type SKIP_DRAM_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    ///Bits 0:11 - PRE_CKE_X1024
19    #[inline(always)]
20    pub fn pre_cke_x1024(&self) -> PRE_CKE_X1024_R {
21        PRE_CKE_X1024_R::new((self.bits & 0x0fff) as u16)
22    }
23    ///Bits 16:25 - POST_CKE_X1024
24    #[inline(always)]
25    pub fn post_cke_x1024(&self) -> POST_CKE_X1024_R {
26        POST_CKE_X1024_R::new(((self.bits >> 16) & 0x03ff) as u16)
27    }
28    ///Bits 30:31 - SKIP_DRAM_INIT
29    #[inline(always)]
30    pub fn skip_dram_init(&self) -> SKIP_DRAM_INIT_R {
31        SKIP_DRAM_INIT_R::new(((self.bits >> 30) & 3) as u8)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("INIT0")
37            .field("pre_cke_x1024", &self.pre_cke_x1024())
38            .field("post_cke_x1024", &self.post_cke_x1024())
39            .field("skip_dram_init", &self.skip_dram_init())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:11 - PRE_CKE_X1024
45    #[inline(always)]
46    pub fn pre_cke_x1024(&mut self) -> PRE_CKE_X1024_W<INIT0rs> {
47        PRE_CKE_X1024_W::new(self, 0)
48    }
49    ///Bits 16:25 - POST_CKE_X1024
50    #[inline(always)]
51    pub fn post_cke_x1024(&mut self) -> POST_CKE_X1024_W<INIT0rs> {
52        POST_CKE_X1024_W::new(self, 16)
53    }
54    ///Bits 30:31 - SKIP_DRAM_INIT
55    #[inline(always)]
56    pub fn skip_dram_init(&mut self) -> SKIP_DRAM_INIT_W<INIT0rs> {
57        SKIP_DRAM_INIT_W::new(self, 30)
58    }
59}
60/**DDRCTRL SDRAM initialization register 0
61
62You can [`read`](crate::Reg::read) this register and get [`init0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`init0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRCTRL:INIT0)*/
65pub struct INIT0rs;
66impl crate::RegisterSpec for INIT0rs {
67    type Ux = u32;
68}
69///`read()` method returns [`init0::R`](R) reader structure
70impl crate::Readable for INIT0rs {}
71///`write(|w| ..)` method takes [`init0::W`](W) writer structure
72impl crate::Writable for INIT0rs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets INIT0 to value 0x0002_004e
76impl crate::Resettable for INIT0rs {
77    const RESET_VALUE: u32 = 0x0002_004e;
78}
stm32mp1/stm32mp157/ddrctrl/init0.rs

stm32mp1/stm32mp157/ddrctrl/
init0.rs
