stm32mp1/stm32mp157/ddrctrl/
dimmctl.rs1pub type R = crate::R<DIMMCTLrs>;
3pub type W = crate::W<DIMMCTLrs>;
5pub type DIMM_STAGGER_CS_EN_R = crate::BitReader;
7pub type DIMM_STAGGER_CS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9pub type DIMM_ADDR_MIRR_EN_R = crate::BitReader;
11pub type DIMM_ADDR_MIRR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14 #[inline(always)]
16 pub fn dimm_stagger_cs_en(&self) -> DIMM_STAGGER_CS_EN_R {
17 DIMM_STAGGER_CS_EN_R::new((self.bits & 1) != 0)
18 }
19 #[inline(always)]
21 pub fn dimm_addr_mirr_en(&self) -> DIMM_ADDR_MIRR_EN_R {
22 DIMM_ADDR_MIRR_EN_R::new(((self.bits >> 1) & 1) != 0)
23 }
24}
25impl core::fmt::Debug for R {
26 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27 f.debug_struct("DIMMCTL")
28 .field("dimm_stagger_cs_en", &self.dimm_stagger_cs_en())
29 .field("dimm_addr_mirr_en", &self.dimm_addr_mirr_en())
30 .finish()
31 }
32}
33impl W {
34 #[inline(always)]
36 pub fn dimm_stagger_cs_en(&mut self) -> DIMM_STAGGER_CS_EN_W<DIMMCTLrs> {
37 DIMM_STAGGER_CS_EN_W::new(self, 0)
38 }
39 #[inline(always)]
41 pub fn dimm_addr_mirr_en(&mut self) -> DIMM_ADDR_MIRR_EN_W<DIMMCTLrs> {
42 DIMM_ADDR_MIRR_EN_W::new(self, 1)
43 }
44}
45pub struct DIMMCTLrs;
51impl crate::RegisterSpec for DIMMCTLrs {
52 type Ux = u32;
53}
54impl crate::Readable for DIMMCTLrs {}
56impl crate::Writable for DIMMCTLrs {
58 type Safety = crate::Unsafe;
59}
60impl crate::Resettable for DIMMCTLrs {}