stm32mp1/stm32mp157/dcmi/
mis.rs

1///Register `MIS` reader
2pub type R = crate::R<MISrs>;
3///Field `FRAME_MIS` reader - FRAME_MIS
4pub type FRAME_MIS_R = crate::BitReader;
5///Field `OVR_MIS` reader - OVR_MIS
6pub type OVR_MIS_R = crate::BitReader;
7///Field `ERR_MIS` reader - ERR_MIS
8pub type ERR_MIS_R = crate::BitReader;
9///Field `VSYNC_MIS` reader - VSYNC_MIS
10pub type VSYNC_MIS_R = crate::BitReader;
11///Field `LINE_MIS` reader - LINE_MIS
12pub type LINE_MIS_R = crate::BitReader;
13impl R {
14    ///Bit 0 - FRAME_MIS
15    #[inline(always)]
16    pub fn frame_mis(&self) -> FRAME_MIS_R {
17        FRAME_MIS_R::new((self.bits & 1) != 0)
18    }
19    ///Bit 1 - OVR_MIS
20    #[inline(always)]
21    pub fn ovr_mis(&self) -> OVR_MIS_R {
22        OVR_MIS_R::new(((self.bits >> 1) & 1) != 0)
23    }
24    ///Bit 2 - ERR_MIS
25    #[inline(always)]
26    pub fn err_mis(&self) -> ERR_MIS_R {
27        ERR_MIS_R::new(((self.bits >> 2) & 1) != 0)
28    }
29    ///Bit 3 - VSYNC_MIS
30    #[inline(always)]
31    pub fn vsync_mis(&self) -> VSYNC_MIS_R {
32        VSYNC_MIS_R::new(((self.bits >> 3) & 1) != 0)
33    }
34    ///Bit 4 - LINE_MIS
35    #[inline(always)]
36    pub fn line_mis(&self) -> LINE_MIS_R {
37        LINE_MIS_R::new(((self.bits >> 4) & 1) != 0)
38    }
39}
40impl core::fmt::Debug for R {
41    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
42        f.debug_struct("MIS")
43            .field("frame_mis", &self.frame_mis())
44            .field("ovr_mis", &self.ovr_mis())
45            .field("err_mis", &self.err_mis())
46            .field("vsync_mis", &self.vsync_mis())
47            .field("line_mis", &self.line_mis())
48            .finish()
49    }
50}
51/**This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
52
53You can [`read`](crate::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
54
55See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DCMI:MIS)*/
56pub struct MISrs;
57impl crate::RegisterSpec for MISrs {
58    type Ux = u32;
59}
60///`read()` method returns [`mis::R`](R) reader structure
61impl crate::Readable for MISrs {}
62///`reset()` method sets MIS to value 0
63impl crate::Resettable for MISrs {}
stm32mp1/stm32mp157/dcmi/mis.rs

stm32mp1/stm32mp157/dcmi/
mis.rs
