Module stm32mp1::stm32mp157::ddrctrl

DDRCTRL

Modules

ddrctrl_addrmap1	DDRCTRL address map register 1
ddrctrl_addrmap2	DDRCTRL address map register 2
ddrctrl_addrmap3	DDRCTRL address map register 3
ddrctrl_addrmap4	DDRCTRL address map register 4
ddrctrl_addrmap5	DDRCTRL address map register 5
ddrctrl_addrmap6	DDRCTRL address register 6
ddrctrl_addrmap9	DDRCTRL address map register 9
ddrctrl_addrmap10	DDRCTRL address map register 10
ddrctrl_addrmap11	DDRCTRL address map register 11
ddrctrl_crcparctl0	DDRCTRL CRC parity control register 0
ddrctrl_crcparstat	DDRCTRL CRC parity status register
ddrctrl_dbg0	DDRCTRL debug register 0
ddrctrl_dbg1	DDRCTRL debug register 1
ddrctrl_dbgcam	DDRCTRL CAM debug register
ddrctrl_dbgcmd	DDRCTRL command debug register
ddrctrl_dbgstat	DDRCTRL status debug register
ddrctrl_derateen	DDRCTRL temperature derate enable register
ddrctrl_derateint	DDRCTRL temperature derate interval register
ddrctrl_dfilpcfg0	DDRCTRL low power configuration register 0
ddrctrl_dfimisc	DDRCTRL DFI miscellaneous control register
ddrctrl_dfiphymstr	DDRCTRL DFI PHY master register
ddrctrl_dfistat	DDRCTRL DFI status register
ddrctrl_dfitmg0	DDRCTRL DFI timing register 0
ddrctrl_dfitmg1	DDRCTRL DFI timing register 1
ddrctrl_dfiupd0	DDRCTRL DFI update register 0
ddrctrl_dfiupd1	DDRCTRL DFI update register 1
ddrctrl_dfiupd2	DDRCTRL DFI update register 2
ddrctrl_dimmctl	DDRCTRL DIMM control register
ddrctrl_dramtmg0	DDRCTRL SDRAM timing register 0
ddrctrl_dramtmg1	DDRCTRL SDRAM timing register 1
ddrctrl_dramtmg2	DDRCTRL SDRAM timing register 2
ddrctrl_dramtmg3	DDRCTRL SDRAM timing register 3
ddrctrl_dramtmg4	DDRCTRL SDRAM timing register 4
ddrctrl_dramtmg5	DDRCTRL SDRAM timing register 5
ddrctrl_dramtmg6	DDRCTRL SDRAM timing register 6
ddrctrl_dramtmg7	DDRCTRL SDRAM timing register 7
ddrctrl_dramtmg8	DDRCTRL SDRAM timing register 8
ddrctrl_dramtmg14	DDRCTRL SDRAM timing register 14
ddrctrl_dramtmg15	DDRCTRL SDRAM timing register 15
ddrctrl_hwlpctl	DDRCTRL hardware low power control register
ddrctrl_init0	DDRCTRL SDRAM initialization register 0
ddrctrl_init1	DDRCTRL SDRAM initialization register 1
ddrctrl_init2	DDRCTRL SDRAM initialization register 2
ddrctrl_init3	DDRCTRL SDRAM initialization register 3
ddrctrl_init4	DDRCTRL SDRAM initialization register 4
ddrctrl_init5	DDRCTRL SDRAM initialization register 5
ddrctrl_mrctrl0	Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en
ddrctrl_mrctrl1	DDRCTRL mode register read/write control register 1
ddrctrl_mrstat	DDRCTRL mode register read/write status register
ddrctrl_mstr	DDRCTRL master register 0
ddrctrl_odtcfg	DDRCTRL ODT configuration register
ddrctrl_odtmap	DDRCTRL ODT/Rank map register
ddrctrl_pccfg	DDRCTRL port common configuration register
ddrctrl_pcfgqos0_0	DDRCTRL port 0 read Q0S configuration register 0
ddrctrl_pcfgqos0_1	DDRCTRL port 1 read Q0S configuration register 0
ddrctrl_pcfgqos1_0	DDRCTRL port 0 read Q0S configuration register 1
ddrctrl_pcfgqos1_1	DDRCTRL port 1 read Q0S configuration register 1
ddrctrl_pcfgr_0	DDRCTRL port 0 configuration read register
ddrctrl_pcfgr_1	DDRCTRL port 1 configuration read register
ddrctrl_pcfgw_0	DDRCTRL port 0 configuration write register
ddrctrl_pcfgw_1	DDRCTRL port 1 configuration write register
ddrctrl_pcfgwqos0_0	DDRCTRL port 0 write Q0S configuration register 0
ddrctrl_pcfgwqos0_1	DDRCTRL port 1 write Q0S configuration register 0
ddrctrl_pcfgwqos1_0	DDRCTRL port 0 write Q0S configuration register 1
ddrctrl_pcfgwqos1_1	DDRCTRL port 1 write Q0S configuration register 1
ddrctrl_pctrl_0	DDRCTRL port 0 control register
ddrctrl_pctrl_1	DDRCTRL port 1 control register
ddrctrl_perfhpr1	DDRCTRL high priority read CAM register 1
ddrctrl_perflpr1	DDRCTRL low priority read CAM register 1
ddrctrl_perfwr1	DDRCTRL write CAM register 1
ddrctrl_poisoncfg	AXI Poison configuration register common for all AXI ports.
ddrctrl_poisonstat	DDRCTRL AXI Poison status register
ddrctrl_pstat	DDRCTRL port status register
ddrctrl_pwrctl	DDRCTRL low power control register
ddrctrl_pwrtmg	DDRCTRL low power timing register
ddrctrl_rfshctl0	DDRCTRL refresh control register 0
ddrctrl_rfshctl3	DDRCTRL refresh control register 3
ddrctrl_rfshtmg	DDRCTRL refresh timing register
ddrctrl_sched	DDRCTRL scheduler control register
ddrctrl_sched1	DDRCTRL scheduler control register 1
ddrctrl_stat	DDRCTRL operating mode status register
ddrctrl_swctl	DDRCTRL software register programming control enable
ddrctrl_swstat	DDRCTRL software register programming control status
ddrctrl_zqctl0	DDRCTRL ZQ control register 0
ddrctrl_zqctl1	DDRCTRL ZQ control register 1
ddrctrl_zqctl2	DDRCTRL ZQ control register 2
ddrctrl_zqstat	DDRCTRL ZQ status register

Structs

RegisterBlock

Register block

Type Definitions

DDRCTRL_ADDRMAP1	DDRCTRL address map register 1
DDRCTRL_ADDRMAP2	DDRCTRL address map register 2
DDRCTRL_ADDRMAP3	DDRCTRL address map register 3
DDRCTRL_ADDRMAP4	DDRCTRL address map register 4
DDRCTRL_ADDRMAP5	DDRCTRL address map register 5
DDRCTRL_ADDRMAP6	DDRCTRL address register 6
DDRCTRL_ADDRMAP9	DDRCTRL address map register 9
DDRCTRL_ADDRMAP10	DDRCTRL address map register 10
DDRCTRL_ADDRMAP11	DDRCTRL address map register 11
DDRCTRL_CRCPARCTL0	DDRCTRL CRC parity control register 0
DDRCTRL_CRCPARSTAT	DDRCTRL CRC parity status register
DDRCTRL_DBG0	DDRCTRL debug register 0
DDRCTRL_DBG1	DDRCTRL debug register 1
DDRCTRL_DBGCAM	DDRCTRL CAM debug register
DDRCTRL_DBGCMD	DDRCTRL command debug register
DDRCTRL_DBGSTAT	DDRCTRL status debug register
DDRCTRL_DERATEEN	DDRCTRL temperature derate enable register
DDRCTRL_DERATEINT	DDRCTRL temperature derate interval register
DDRCTRL_DFILPCFG0	DDRCTRL low power configuration register 0
DDRCTRL_DFIMISC	DDRCTRL DFI miscellaneous control register
DDRCTRL_DFIPHYMSTR	DDRCTRL DFI PHY master register
DDRCTRL_DFISTAT	DDRCTRL DFI status register
DDRCTRL_DFITMG0	DDRCTRL DFI timing register 0
DDRCTRL_DFITMG1	DDRCTRL DFI timing register 1
DDRCTRL_DFIUPD0	DDRCTRL DFI update register 0
DDRCTRL_DFIUPD1	DDRCTRL DFI update register 1
DDRCTRL_DFIUPD2	DDRCTRL DFI update register 2
DDRCTRL_DIMMCTL	DDRCTRL DIMM control register
DDRCTRL_DRAMTMG0	DDRCTRL SDRAM timing register 0
DDRCTRL_DRAMTMG1	DDRCTRL SDRAM timing register 1
DDRCTRL_DRAMTMG2	DDRCTRL SDRAM timing register 2
DDRCTRL_DRAMTMG3	DDRCTRL SDRAM timing register 3
DDRCTRL_DRAMTMG4	DDRCTRL SDRAM timing register 4
DDRCTRL_DRAMTMG5	DDRCTRL SDRAM timing register 5
DDRCTRL_DRAMTMG6	DDRCTRL SDRAM timing register 6
DDRCTRL_DRAMTMG7	DDRCTRL SDRAM timing register 7
DDRCTRL_DRAMTMG8	DDRCTRL SDRAM timing register 8
DDRCTRL_DRAMTMG14	DDRCTRL SDRAM timing register 14
DDRCTRL_DRAMTMG15	DDRCTRL SDRAM timing register 15
DDRCTRL_HWLPCTL	DDRCTRL hardware low power control register
DDRCTRL_INIT0	DDRCTRL SDRAM initialization register 0
DDRCTRL_INIT1	DDRCTRL SDRAM initialization register 1
DDRCTRL_INIT2	DDRCTRL SDRAM initialization register 2
DDRCTRL_INIT3	DDRCTRL SDRAM initialization register 3
DDRCTRL_INIT4	DDRCTRL SDRAM initialization register 4
DDRCTRL_INIT5	DDRCTRL SDRAM initialization register 5
DDRCTRL_MRCTRL0	Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en
DDRCTRL_MRCTRL1	DDRCTRL mode register read/write control register 1
DDRCTRL_MRSTAT	DDRCTRL mode register read/write status register
DDRCTRL_MSTR	DDRCTRL master register 0
DDRCTRL_ODTCFG	DDRCTRL ODT configuration register
DDRCTRL_ODTMAP	DDRCTRL ODT/Rank map register
DDRCTRL_PCCFG	DDRCTRL port common configuration register
DDRCTRL_PCFGQOS0_0	DDRCTRL port 0 read Q0S configuration register 0
DDRCTRL_PCFGQOS0_1	DDRCTRL port 1 read Q0S configuration register 0
DDRCTRL_PCFGQOS1_0	DDRCTRL port 0 read Q0S configuration register 1
DDRCTRL_PCFGQOS1_1	DDRCTRL port 1 read Q0S configuration register 1
DDRCTRL_PCFGR_0	DDRCTRL port 0 configuration read register
DDRCTRL_PCFGR_1	DDRCTRL port 1 configuration read register
DDRCTRL_PCFGWQOS0_0	DDRCTRL port 0 write Q0S configuration register 0
DDRCTRL_PCFGWQOS0_1	DDRCTRL port 1 write Q0S configuration register 0
DDRCTRL_PCFGWQOS1_0	DDRCTRL port 0 write Q0S configuration register 1
DDRCTRL_PCFGWQOS1_1	DDRCTRL port 1 write Q0S configuration register 1
DDRCTRL_PCFGW_0	DDRCTRL port 0 configuration write register
DDRCTRL_PCFGW_1	DDRCTRL port 1 configuration write register
DDRCTRL_PCTRL_0	DDRCTRL port 0 control register
DDRCTRL_PCTRL_1	DDRCTRL port 1 control register
DDRCTRL_PERFHPR1	DDRCTRL high priority read CAM register 1
DDRCTRL_PERFLPR1	DDRCTRL low priority read CAM register 1
DDRCTRL_PERFWR1	DDRCTRL write CAM register 1
DDRCTRL_POISONCFG	AXI Poison configuration register common for all AXI ports.
DDRCTRL_POISONSTAT	DDRCTRL AXI Poison status register
DDRCTRL_PSTAT	DDRCTRL port status register
DDRCTRL_PWRCTL	DDRCTRL low power control register
DDRCTRL_PWRTMG	DDRCTRL low power timing register
DDRCTRL_RFSHCTL0	DDRCTRL refresh control register 0
DDRCTRL_RFSHCTL3	DDRCTRL refresh control register 3
DDRCTRL_RFSHTMG	DDRCTRL refresh timing register
DDRCTRL_SCHED	DDRCTRL scheduler control register
DDRCTRL_SCHED1	DDRCTRL scheduler control register 1
DDRCTRL_STAT	DDRCTRL operating mode status register
DDRCTRL_SWCTL	DDRCTRL software register programming control enable
DDRCTRL_SWSTAT	DDRCTRL software register programming control status
DDRCTRL_ZQCTL0	DDRCTRL ZQ control register 0
DDRCTRL_ZQCTL1	DDRCTRL ZQ control register 1
DDRCTRL_ZQCTL2	DDRCTRL ZQ control register 2
DDRCTRL_ZQSTAT	DDRCTRL ZQ status register