stm32l5/stm32l562/tim2/
ccmr1_output.rs

1///Register `CCMR1_Output` reader
2pub type R = crate::R<CCMR1_OUTPUTrs>;
3///Register `CCMR1_Output` writer
4pub type W = crate::W<CCMR1_OUTPUTrs>;
5/**Capture/Compare %s selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum CC1S {
12    ///0: CCx channel is configured as output
13    Output = 0,
14}
15impl From<CC1S> for u8 {
16    #[inline(always)]
17    fn from(variant: CC1S) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for CC1S {
22    type Ux = u8;
23}
24impl crate::IsEnum for CC1S {}
25///Field `CCS(1-2)` reader - Capture/Compare %s selection
26pub type CCS_R = crate::FieldReader<CC1S>;
27impl CCS_R {
28    ///Get enumerated values variant
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<CC1S> {
31        match self.bits {
32            0 => Some(CC1S::Output),
33            _ => None,
34        }
35    }
36    ///CCx channel is configured as output
37    #[inline(always)]
38    pub fn is_output(&self) -> bool {
39        *self == CC1S::Output
40    }
41}
42///Field `CCS(1-2)` writer - Capture/Compare %s selection
43pub type CCS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC1S>;
44impl<'a, REG> CCS_W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47    REG::Ux: From<u8>,
48{
49    ///CCx channel is configured as output
50    #[inline(always)]
51    pub fn output(self) -> &'a mut crate::W<REG> {
52        self.variant(CC1S::Output)
53    }
54}
55/**Output compare %s fast enable
56
57Value on reset: 0*/
58#[cfg_attr(feature = "defmt", derive(defmt::Format))]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum OC1FE {
61    ///0: Fast output disabled
62    Disabled = 0,
63    ///1: Fast output enabled
64    Enabled = 1,
65}
66impl From<OC1FE> for bool {
67    #[inline(always)]
68    fn from(variant: OC1FE) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `OCFE(1-2)` reader - Output compare %s fast enable
73pub type OCFE_R = crate::BitReader<OC1FE>;
74impl OCFE_R {
75    ///Get enumerated values variant
76    #[inline(always)]
77    pub const fn variant(&self) -> OC1FE {
78        match self.bits {
79            false => OC1FE::Disabled,
80            true => OC1FE::Enabled,
81        }
82    }
83    ///Fast output disabled
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == OC1FE::Disabled
87    }
88    ///Fast output enabled
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == OC1FE::Enabled
92    }
93}
94///Field `OCFE(1-2)` writer - Output compare %s fast enable
95pub type OCFE_W<'a, REG> = crate::BitWriter<'a, REG, OC1FE>;
96impl<'a, REG> OCFE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    ///Fast output disabled
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(OC1FE::Disabled)
104    }
105    ///Fast output enabled
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(OC1FE::Enabled)
109    }
110}
111/**Output compare %s preload enable
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum OC1PE {
117    ///0: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
118    Disabled = 0,
119    ///1: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
120    Enabled = 1,
121}
122impl From<OC1PE> for bool {
123    #[inline(always)]
124    fn from(variant: OC1PE) -> Self {
125        variant as u8 != 0
126    }
127}
128///Field `OCPE(1-2)` reader - Output compare %s preload enable
129pub type OCPE_R = crate::BitReader<OC1PE>;
130impl OCPE_R {
131    ///Get enumerated values variant
132    #[inline(always)]
133    pub const fn variant(&self) -> OC1PE {
134        match self.bits {
135            false => OC1PE::Disabled,
136            true => OC1PE::Enabled,
137        }
138    }
139    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == OC1PE::Disabled
143    }
144    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == OC1PE::Enabled
148    }
149}
150///Field `OCPE(1-2)` writer - Output compare %s preload enable
151pub type OCPE_W<'a, REG> = crate::BitWriter<'a, REG, OC1PE>;
152impl<'a, REG> OCPE_W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(OC1PE::Disabled)
160    }
161    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(OC1PE::Enabled)
165    }
166}
167/**Output compare %s mode
168
169Value on reset: 0*/
170#[cfg_attr(feature = "defmt", derive(defmt::Format))]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum OC1M {
174    ///0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
175    Frozen = 0,
176    ///1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
177    ActiveOnMatch = 1,
178    ///2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
179    InactiveOnMatch = 2,
180    ///3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
181    Toggle = 3,
182    ///4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
183    ForceInactive = 4,
184    ///5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
185    ForceActive = 5,
186    ///6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
187    PwmMode1 = 6,
188    ///7: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
189    PwmMode2 = 7,
190}
191impl From<OC1M> for u8 {
192    #[inline(always)]
193    fn from(variant: OC1M) -> Self {
194        variant as _
195    }
196}
197impl crate::FieldSpec for OC1M {
198    type Ux = u8;
199}
200impl crate::IsEnum for OC1M {}
201///Field `OCM(1-2)` reader - Output compare %s mode
202pub type OCM_R = crate::FieldReader<OC1M>;
203impl OCM_R {
204    ///Get enumerated values variant
205    #[inline(always)]
206    pub const fn variant(&self) -> OC1M {
207        match self.bits {
208            0 => OC1M::Frozen,
209            1 => OC1M::ActiveOnMatch,
210            2 => OC1M::InactiveOnMatch,
211            3 => OC1M::Toggle,
212            4 => OC1M::ForceInactive,
213            5 => OC1M::ForceActive,
214            6 => OC1M::PwmMode1,
215            7 => OC1M::PwmMode2,
216            _ => unreachable!(),
217        }
218    }
219    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
220    #[inline(always)]
221    pub fn is_frozen(&self) -> bool {
222        *self == OC1M::Frozen
223    }
224    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
225    #[inline(always)]
226    pub fn is_active_on_match(&self) -> bool {
227        *self == OC1M::ActiveOnMatch
228    }
229    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
230    #[inline(always)]
231    pub fn is_inactive_on_match(&self) -> bool {
232        *self == OC1M::InactiveOnMatch
233    }
234    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
235    #[inline(always)]
236    pub fn is_toggle(&self) -> bool {
237        *self == OC1M::Toggle
238    }
239    ///OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
240    #[inline(always)]
241    pub fn is_force_inactive(&self) -> bool {
242        *self == OC1M::ForceInactive
243    }
244    ///OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
245    #[inline(always)]
246    pub fn is_force_active(&self) -> bool {
247        *self == OC1M::ForceActive
248    }
249    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
250    #[inline(always)]
251    pub fn is_pwm_mode1(&self) -> bool {
252        *self == OC1M::PwmMode1
253    }
254    ///Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
255    #[inline(always)]
256    pub fn is_pwm_mode2(&self) -> bool {
257        *self == OC1M::PwmMode2
258    }
259}
260///Field `OCM(1-2)` writer - Output compare %s mode
261pub type OCM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OC1M, crate::Safe>;
262impl<'a, REG> OCM_W<'a, REG>
263where
264    REG: crate::Writable + crate::RegisterSpec,
265    REG::Ux: From<u8>,
266{
267    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
268    #[inline(always)]
269    pub fn frozen(self) -> &'a mut crate::W<REG> {
270        self.variant(OC1M::Frozen)
271    }
272    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
273    #[inline(always)]
274    pub fn active_on_match(self) -> &'a mut crate::W<REG> {
275        self.variant(OC1M::ActiveOnMatch)
276    }
277    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
278    #[inline(always)]
279    pub fn inactive_on_match(self) -> &'a mut crate::W<REG> {
280        self.variant(OC1M::InactiveOnMatch)
281    }
282    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
283    #[inline(always)]
284    pub fn toggle(self) -> &'a mut crate::W<REG> {
285        self.variant(OC1M::Toggle)
286    }
287    ///OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
288    #[inline(always)]
289    pub fn force_inactive(self) -> &'a mut crate::W<REG> {
290        self.variant(OC1M::ForceInactive)
291    }
292    ///OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
293    #[inline(always)]
294    pub fn force_active(self) -> &'a mut crate::W<REG> {
295        self.variant(OC1M::ForceActive)
296    }
297    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
298    #[inline(always)]
299    pub fn pwm_mode1(self) -> &'a mut crate::W<REG> {
300        self.variant(OC1M::PwmMode1)
301    }
302    ///Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
303    #[inline(always)]
304    pub fn pwm_mode2(self) -> &'a mut crate::W<REG> {
305        self.variant(OC1M::PwmMode2)
306    }
307}
308/**Output compare %s clear enable
309
310Value on reset: 0*/
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum OC1CE {
314    ///0: OCxRef is not affected by the ETRF signal
315    Disabled = 0,
316    ///1: OCxRef is cleared as soon as a High level is detected on ETRF signal
317    Enabled = 1,
318}
319impl From<OC1CE> for bool {
320    #[inline(always)]
321    fn from(variant: OC1CE) -> Self {
322        variant as u8 != 0
323    }
324}
325///Field `OCCE(1-2)` reader - Output compare %s clear enable
326pub type OCCE_R = crate::BitReader<OC1CE>;
327impl OCCE_R {
328    ///Get enumerated values variant
329    #[inline(always)]
330    pub const fn variant(&self) -> OC1CE {
331        match self.bits {
332            false => OC1CE::Disabled,
333            true => OC1CE::Enabled,
334        }
335    }
336    ///OCxRef is not affected by the ETRF signal
337    #[inline(always)]
338    pub fn is_disabled(&self) -> bool {
339        *self == OC1CE::Disabled
340    }
341    ///OCxRef is cleared as soon as a High level is detected on ETRF signal
342    #[inline(always)]
343    pub fn is_enabled(&self) -> bool {
344        *self == OC1CE::Enabled
345    }
346}
347///Field `OCCE(1-2)` writer - Output compare %s clear enable
348pub type OCCE_W<'a, REG> = crate::BitWriter<'a, REG, OC1CE>;
349impl<'a, REG> OCCE_W<'a, REG>
350where
351    REG: crate::Writable + crate::RegisterSpec,
352{
353    ///OCxRef is not affected by the ETRF signal
354    #[inline(always)]
355    pub fn disabled(self) -> &'a mut crate::W<REG> {
356        self.variant(OC1CE::Disabled)
357    }
358    ///OCxRef is cleared as soon as a High level is detected on ETRF signal
359    #[inline(always)]
360    pub fn enabled(self) -> &'a mut crate::W<REG> {
361        self.variant(OC1CE::Enabled)
362    }
363}
364/**Output compare %s mode, bit 3
365
366Value on reset: 0*/
367#[cfg_attr(feature = "defmt", derive(defmt::Format))]
368#[derive(Clone, Copy, Debug, PartialEq, Eq)]
369pub enum OC1M_3 {
370    ///0: Normal output compare mode (modes 0-7)
371    Normal = 0,
372    ///1: Extended output compare mode (modes 7-15)
373    Extended = 1,
374}
375impl From<OC1M_3> for bool {
376    #[inline(always)]
377    fn from(variant: OC1M_3) -> Self {
378        variant as u8 != 0
379    }
380}
381///Field `OCM_3(1-2)` reader - Output compare %s mode, bit 3
382pub type OCM_3_R = crate::BitReader<OC1M_3>;
383impl OCM_3_R {
384    ///Get enumerated values variant
385    #[inline(always)]
386    pub const fn variant(&self) -> OC1M_3 {
387        match self.bits {
388            false => OC1M_3::Normal,
389            true => OC1M_3::Extended,
390        }
391    }
392    ///Normal output compare mode (modes 0-7)
393    #[inline(always)]
394    pub fn is_normal(&self) -> bool {
395        *self == OC1M_3::Normal
396    }
397    ///Extended output compare mode (modes 7-15)
398    #[inline(always)]
399    pub fn is_extended(&self) -> bool {
400        *self == OC1M_3::Extended
401    }
402}
403///Field `OCM_3(1-2)` writer - Output compare %s mode, bit 3
404pub type OCM_3_W<'a, REG> = crate::BitWriter<'a, REG, OC1M_3>;
405impl<'a, REG> OCM_3_W<'a, REG>
406where
407    REG: crate::Writable + crate::RegisterSpec,
408{
409    ///Normal output compare mode (modes 0-7)
410    #[inline(always)]
411    pub fn normal(self) -> &'a mut crate::W<REG> {
412        self.variant(OC1M_3::Normal)
413    }
414    ///Extended output compare mode (modes 7-15)
415    #[inline(always)]
416    pub fn extended(self) -> &'a mut crate::W<REG> {
417        self.variant(OC1M_3::Extended)
418    }
419}
420impl R {
421    ///Capture/Compare (1-2) selection
422    ///
423    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1S` field.</div>
424    #[inline(always)]
425    pub fn ccs(&self, n: u8) -> CCS_R {
426        #[allow(clippy::no_effect)]
427        [(); 2][n as usize];
428        CCS_R::new(((self.bits >> (n * 8)) & 3) as u8)
429    }
430    ///Iterator for array of:
431    ///Capture/Compare (1-2) selection
432    #[inline(always)]
433    pub fn ccs_iter(&self) -> impl Iterator<Item = CCS_R> + '_ {
434        (0..2).map(move |n| CCS_R::new(((self.bits >> (n * 8)) & 3) as u8))
435    }
436    ///Bits 0:1 - Capture/Compare 1 selection
437    #[inline(always)]
438    pub fn cc1s(&self) -> CCS_R {
439        CCS_R::new((self.bits & 3) as u8)
440    }
441    ///Bits 8:9 - Capture/Compare 2 selection
442    #[inline(always)]
443    pub fn cc2s(&self) -> CCS_R {
444        CCS_R::new(((self.bits >> 8) & 3) as u8)
445    }
446    ///Output compare (1-2) fast enable
447    ///
448    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1FE` field.</div>
449    #[inline(always)]
450    pub fn ocfe(&self, n: u8) -> OCFE_R {
451        #[allow(clippy::no_effect)]
452        [(); 2][n as usize];
453        OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0)
454    }
455    ///Iterator for array of:
456    ///Output compare (1-2) fast enable
457    #[inline(always)]
458    pub fn ocfe_iter(&self) -> impl Iterator<Item = OCFE_R> + '_ {
459        (0..2).map(move |n| OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0))
460    }
461    ///Bit 2 - Output compare 1 fast enable
462    #[inline(always)]
463    pub fn oc1fe(&self) -> OCFE_R {
464        OCFE_R::new(((self.bits >> 2) & 1) != 0)
465    }
466    ///Bit 10 - Output compare 2 fast enable
467    #[inline(always)]
468    pub fn oc2fe(&self) -> OCFE_R {
469        OCFE_R::new(((self.bits >> 10) & 1) != 0)
470    }
471    ///Output compare (1-2) preload enable
472    ///
473    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1PE` field.</div>
474    #[inline(always)]
475    pub fn ocpe(&self, n: u8) -> OCPE_R {
476        #[allow(clippy::no_effect)]
477        [(); 2][n as usize];
478        OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0)
479    }
480    ///Iterator for array of:
481    ///Output compare (1-2) preload enable
482    #[inline(always)]
483    pub fn ocpe_iter(&self) -> impl Iterator<Item = OCPE_R> + '_ {
484        (0..2).map(move |n| OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0))
485    }
486    ///Bit 3 - Output compare 1 preload enable
487    #[inline(always)]
488    pub fn oc1pe(&self) -> OCPE_R {
489        OCPE_R::new(((self.bits >> 3) & 1) != 0)
490    }
491    ///Bit 11 - Output compare 2 preload enable
492    #[inline(always)]
493    pub fn oc2pe(&self) -> OCPE_R {
494        OCPE_R::new(((self.bits >> 11) & 1) != 0)
495    }
496    ///Output compare (1-2) mode
497    ///
498    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M` field.</div>
499    #[inline(always)]
500    pub fn ocm(&self, n: u8) -> OCM_R {
501        #[allow(clippy::no_effect)]
502        [(); 2][n as usize];
503        OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8)
504    }
505    ///Iterator for array of:
506    ///Output compare (1-2) mode
507    #[inline(always)]
508    pub fn ocm_iter(&self) -> impl Iterator<Item = OCM_R> + '_ {
509        (0..2).map(move |n| OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8))
510    }
511    ///Bits 4:6 - Output compare 1 mode
512    #[inline(always)]
513    pub fn oc1m(&self) -> OCM_R {
514        OCM_R::new(((self.bits >> 4) & 7) as u8)
515    }
516    ///Bits 12:14 - Output compare 2 mode
517    #[inline(always)]
518    pub fn oc2m(&self) -> OCM_R {
519        OCM_R::new(((self.bits >> 12) & 7) as u8)
520    }
521    ///Output compare (1-2) clear enable
522    ///
523    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1CE` field.</div>
524    #[inline(always)]
525    pub fn occe(&self, n: u8) -> OCCE_R {
526        #[allow(clippy::no_effect)]
527        [(); 2][n as usize];
528        OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0)
529    }
530    ///Iterator for array of:
531    ///Output compare (1-2) clear enable
532    #[inline(always)]
533    pub fn occe_iter(&self) -> impl Iterator<Item = OCCE_R> + '_ {
534        (0..2).map(move |n| OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0))
535    }
536    ///Bit 7 - Output compare 1 clear enable
537    #[inline(always)]
538    pub fn oc1ce(&self) -> OCCE_R {
539        OCCE_R::new(((self.bits >> 7) & 1) != 0)
540    }
541    ///Bit 15 - Output compare 2 clear enable
542    #[inline(always)]
543    pub fn oc2ce(&self) -> OCCE_R {
544        OCCE_R::new(((self.bits >> 15) & 1) != 0)
545    }
546    ///Output compare (1-2) mode, bit 3
547    ///
548    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M_3` field.</div>
549    #[inline(always)]
550    pub fn ocm_3(&self, n: u8) -> OCM_3_R {
551        #[allow(clippy::no_effect)]
552        [(); 2][n as usize];
553        OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0)
554    }
555    ///Iterator for array of:
556    ///Output compare (1-2) mode, bit 3
557    #[inline(always)]
558    pub fn ocm_3_iter(&self) -> impl Iterator<Item = OCM_3_R> + '_ {
559        (0..2).map(move |n| OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0))
560    }
561    ///Bit 16 - Output compare 1 mode, bit 3
562    #[inline(always)]
563    pub fn oc1m_3(&self) -> OCM_3_R {
564        OCM_3_R::new(((self.bits >> 16) & 1) != 0)
565    }
566    ///Bit 24 - Output compare 2 mode, bit 3
567    #[inline(always)]
568    pub fn oc2m_3(&self) -> OCM_3_R {
569        OCM_3_R::new(((self.bits >> 24) & 1) != 0)
570    }
571}
572impl core::fmt::Debug for R {
573    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
574        f.debug_struct("CCMR1_Output")
575            .field("oc1ce", &self.oc1ce())
576            .field("oc2ce", &self.oc2ce())
577            .field("oc1m", &self.oc1m())
578            .field("oc2m", &self.oc2m())
579            .field("oc1pe", &self.oc1pe())
580            .field("oc2pe", &self.oc2pe())
581            .field("oc1fe", &self.oc1fe())
582            .field("oc2fe", &self.oc2fe())
583            .field("cc1s", &self.cc1s())
584            .field("cc2s", &self.cc2s())
585            .field("oc1m_3", &self.oc1m_3())
586            .field("oc2m_3", &self.oc2m_3())
587            .finish()
588    }
589}
590impl W {
591    ///Capture/Compare (1-2) selection
592    ///
593    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1S` field.</div>
594    #[inline(always)]
595    pub fn ccs(&mut self, n: u8) -> CCS_W<CCMR1_OUTPUTrs> {
596        #[allow(clippy::no_effect)]
597        [(); 2][n as usize];
598        CCS_W::new(self, n * 8)
599    }
600    ///Bits 0:1 - Capture/Compare 1 selection
601    #[inline(always)]
602    pub fn cc1s(&mut self) -> CCS_W<CCMR1_OUTPUTrs> {
603        CCS_W::new(self, 0)
604    }
605    ///Bits 8:9 - Capture/Compare 2 selection
606    #[inline(always)]
607    pub fn cc2s(&mut self) -> CCS_W<CCMR1_OUTPUTrs> {
608        CCS_W::new(self, 8)
609    }
610    ///Output compare (1-2) fast enable
611    ///
612    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1FE` field.</div>
613    #[inline(always)]
614    pub fn ocfe(&mut self, n: u8) -> OCFE_W<CCMR1_OUTPUTrs> {
615        #[allow(clippy::no_effect)]
616        [(); 2][n as usize];
617        OCFE_W::new(self, n * 8 + 2)
618    }
619    ///Bit 2 - Output compare 1 fast enable
620    #[inline(always)]
621    pub fn oc1fe(&mut self) -> OCFE_W<CCMR1_OUTPUTrs> {
622        OCFE_W::new(self, 2)
623    }
624    ///Bit 10 - Output compare 2 fast enable
625    #[inline(always)]
626    pub fn oc2fe(&mut self) -> OCFE_W<CCMR1_OUTPUTrs> {
627        OCFE_W::new(self, 10)
628    }
629    ///Output compare (1-2) preload enable
630    ///
631    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1PE` field.</div>
632    #[inline(always)]
633    pub fn ocpe(&mut self, n: u8) -> OCPE_W<CCMR1_OUTPUTrs> {
634        #[allow(clippy::no_effect)]
635        [(); 2][n as usize];
636        OCPE_W::new(self, n * 8 + 3)
637    }
638    ///Bit 3 - Output compare 1 preload enable
639    #[inline(always)]
640    pub fn oc1pe(&mut self) -> OCPE_W<CCMR1_OUTPUTrs> {
641        OCPE_W::new(self, 3)
642    }
643    ///Bit 11 - Output compare 2 preload enable
644    #[inline(always)]
645    pub fn oc2pe(&mut self) -> OCPE_W<CCMR1_OUTPUTrs> {
646        OCPE_W::new(self, 11)
647    }
648    ///Output compare (1-2) mode
649    ///
650    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M` field.</div>
651    #[inline(always)]
652    pub fn ocm(&mut self, n: u8) -> OCM_W<CCMR1_OUTPUTrs> {
653        #[allow(clippy::no_effect)]
654        [(); 2][n as usize];
655        OCM_W::new(self, n * 8 + 4)
656    }
657    ///Bits 4:6 - Output compare 1 mode
658    #[inline(always)]
659    pub fn oc1m(&mut self) -> OCM_W<CCMR1_OUTPUTrs> {
660        OCM_W::new(self, 4)
661    }
662    ///Bits 12:14 - Output compare 2 mode
663    #[inline(always)]
664    pub fn oc2m(&mut self) -> OCM_W<CCMR1_OUTPUTrs> {
665        OCM_W::new(self, 12)
666    }
667    ///Output compare (1-2) clear enable
668    ///
669    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1CE` field.</div>
670    #[inline(always)]
671    pub fn occe(&mut self, n: u8) -> OCCE_W<CCMR1_OUTPUTrs> {
672        #[allow(clippy::no_effect)]
673        [(); 2][n as usize];
674        OCCE_W::new(self, n * 8 + 7)
675    }
676    ///Bit 7 - Output compare 1 clear enable
677    #[inline(always)]
678    pub fn oc1ce(&mut self) -> OCCE_W<CCMR1_OUTPUTrs> {
679        OCCE_W::new(self, 7)
680    }
681    ///Bit 15 - Output compare 2 clear enable
682    #[inline(always)]
683    pub fn oc2ce(&mut self) -> OCCE_W<CCMR1_OUTPUTrs> {
684        OCCE_W::new(self, 15)
685    }
686    ///Output compare (1-2) mode, bit 3
687    ///
688    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M_3` field.</div>
689    #[inline(always)]
690    pub fn ocm_3(&mut self, n: u8) -> OCM_3_W<CCMR1_OUTPUTrs> {
691        #[allow(clippy::no_effect)]
692        [(); 2][n as usize];
693        OCM_3_W::new(self, n * 8 + 16)
694    }
695    ///Bit 16 - Output compare 1 mode, bit 3
696    #[inline(always)]
697    pub fn oc1m_3(&mut self) -> OCM_3_W<CCMR1_OUTPUTrs> {
698        OCM_3_W::new(self, 16)
699    }
700    ///Bit 24 - Output compare 2 mode, bit 3
701    #[inline(always)]
702    pub fn oc2m_3(&mut self) -> OCM_3_W<CCMR1_OUTPUTrs> {
703        OCM_3_W::new(self, 24)
704    }
705}
706/**capture/compare mode register 1 (output mode)
707
708You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
709
710See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L562.html#TIM2:CCMR1_Output)*/
711pub struct CCMR1_OUTPUTrs;
712impl crate::RegisterSpec for CCMR1_OUTPUTrs {
713    type Ux = u32;
714}
715///`read()` method returns [`ccmr1_output::R`](R) reader structure
716impl crate::Readable for CCMR1_OUTPUTrs {}
717///`write(|w| ..)` method takes [`ccmr1_output::W`](W) writer structure
718impl crate::Writable for CCMR1_OUTPUTrs {
719    type Safety = crate::Unsafe;
720}
721///`reset()` method sets CCMR1_Output to value 0
722impl crate::Resettable for CCMR1_OUTPUTrs {}
stm32l5/stm32l562/tim2/ccmr1_output.rs

stm32l5/stm32l562/tim2/
ccmr1_output.rs
