stm32l5/stm32l562/lptim1/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**LPTIM Enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ENABLE {
11    ///0: LPTIM is disabled
12    Disabled = 0,
13    ///1: LPTIM is enabled
14    Enabled = 1,
15}
16impl From<ENABLE> for bool {
17    #[inline(always)]
18    fn from(variant: ENABLE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ENABLE` reader - LPTIM Enable
23pub type ENABLE_R = crate::BitReader<ENABLE>;
24impl ENABLE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ENABLE {
28        match self.bits {
29            false => ENABLE::Disabled,
30            true => ENABLE::Enabled,
31        }
32    }
33    ///LPTIM is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ENABLE::Disabled
37    }
38    ///LPTIM is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ENABLE::Enabled
42    }
43}
44///Field `ENABLE` writer - LPTIM Enable
45pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE>;
46impl<'a, REG> ENABLE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///LPTIM is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(ENABLE::Disabled)
54    }
55    ///LPTIM is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(ENABLE::Enabled)
59    }
60}
61/**LPTIM start in single mode
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum SNGSTRTW {
67    ///1: LPTIM start in Single mode
68    Start = 1,
69}
70impl From<SNGSTRTW> for bool {
71    #[inline(always)]
72    fn from(variant: SNGSTRTW) -> Self {
73        variant as u8 != 0
74    }
75}
76///Field `SNGSTRT` reader - LPTIM start in single mode
77pub type SNGSTRT_R = crate::BitReader<SNGSTRTW>;
78impl SNGSTRT_R {
79    ///Get enumerated values variant
80    #[inline(always)]
81    pub const fn variant(&self) -> Option<SNGSTRTW> {
82        match self.bits {
83            true => Some(SNGSTRTW::Start),
84            _ => None,
85        }
86    }
87    ///LPTIM start in Single mode
88    #[inline(always)]
89    pub fn is_start(&self) -> bool {
90        *self == SNGSTRTW::Start
91    }
92}
93///Field `SNGSTRT` writer - LPTIM start in single mode
94pub type SNGSTRT_W<'a, REG> = crate::BitWriter<'a, REG, SNGSTRTW>;
95impl<'a, REG> SNGSTRT_W<'a, REG>
96where
97    REG: crate::Writable + crate::RegisterSpec,
98{
99    ///LPTIM start in Single mode
100    #[inline(always)]
101    pub fn start(self) -> &'a mut crate::W<REG> {
102        self.variant(SNGSTRTW::Start)
103    }
104}
105/**Timer start in continuous mode
106
107Value on reset: 0*/
108#[cfg_attr(feature = "defmt", derive(defmt::Format))]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum CNTSTRTW {
111    ///1: Timer start in Continuous mode
112    Start = 1,
113}
114impl From<CNTSTRTW> for bool {
115    #[inline(always)]
116    fn from(variant: CNTSTRTW) -> Self {
117        variant as u8 != 0
118    }
119}
120///Field `CNTSTRT` reader - Timer start in continuous mode
121pub type CNTSTRT_R = crate::BitReader<CNTSTRTW>;
122impl CNTSTRT_R {
123    ///Get enumerated values variant
124    #[inline(always)]
125    pub const fn variant(&self) -> Option<CNTSTRTW> {
126        match self.bits {
127            true => Some(CNTSTRTW::Start),
128            _ => None,
129        }
130    }
131    ///Timer start in Continuous mode
132    #[inline(always)]
133    pub fn is_start(&self) -> bool {
134        *self == CNTSTRTW::Start
135    }
136}
137///Field `CNTSTRT` writer - Timer start in continuous mode
138pub type CNTSTRT_W<'a, REG> = crate::BitWriter<'a, REG, CNTSTRTW>;
139impl<'a, REG> CNTSTRT_W<'a, REG>
140where
141    REG: crate::Writable + crate::RegisterSpec,
142{
143    ///Timer start in Continuous mode
144    #[inline(always)]
145    pub fn start(self) -> &'a mut crate::W<REG> {
146        self.variant(CNTSTRTW::Start)
147    }
148}
149/**Reset after read enable
150
151Value on reset: 0*/
152#[cfg_attr(feature = "defmt", derive(defmt::Format))]
153#[derive(Clone, Copy, Debug, PartialEq, Eq)]
154pub enum RSTARE {
155    ///0: CNT Register reads do not trigger reset
156    Disabled = 0,
157    ///1: CNT Register reads trigger reset of LPTIM
158    Enabled = 1,
159}
160impl From<RSTARE> for bool {
161    #[inline(always)]
162    fn from(variant: RSTARE) -> Self {
163        variant as u8 != 0
164    }
165}
166///Field `RSTARE` reader - Reset after read enable
167pub type RSTARE_R = crate::BitReader<RSTARE>;
168impl RSTARE_R {
169    ///Get enumerated values variant
170    #[inline(always)]
171    pub const fn variant(&self) -> RSTARE {
172        match self.bits {
173            false => RSTARE::Disabled,
174            true => RSTARE::Enabled,
175        }
176    }
177    ///CNT Register reads do not trigger reset
178    #[inline(always)]
179    pub fn is_disabled(&self) -> bool {
180        *self == RSTARE::Disabled
181    }
182    ///CNT Register reads trigger reset of LPTIM
183    #[inline(always)]
184    pub fn is_enabled(&self) -> bool {
185        *self == RSTARE::Enabled
186    }
187}
188///Field `RSTARE` writer - Reset after read enable
189pub type RSTARE_W<'a, REG> = crate::BitWriter<'a, REG, RSTARE>;
190impl<'a, REG> RSTARE_W<'a, REG>
191where
192    REG: crate::Writable + crate::RegisterSpec,
193{
194    ///CNT Register reads do not trigger reset
195    #[inline(always)]
196    pub fn disabled(self) -> &'a mut crate::W<REG> {
197        self.variant(RSTARE::Disabled)
198    }
199    ///CNT Register reads trigger reset of LPTIM
200    #[inline(always)]
201    pub fn enabled(self) -> &'a mut crate::W<REG> {
202        self.variant(RSTARE::Enabled)
203    }
204}
205/**Counter reset
206
207Value on reset: 0*/
208#[cfg_attr(feature = "defmt", derive(defmt::Format))]
209#[derive(Clone, Copy, Debug, PartialEq, Eq)]
210pub enum COUNTRSTR {
211    ///0: Triggering of reset is possible
212    Idle = 0,
213    ///1: Reset in progress, do not write 1 to this field
214    Busy = 1,
215}
216impl From<COUNTRSTR> for bool {
217    #[inline(always)]
218    fn from(variant: COUNTRSTR) -> Self {
219        variant as u8 != 0
220    }
221}
222///Field `COUNTRST` reader - Counter reset
223pub type COUNTRST_R = crate::BitReader<COUNTRSTR>;
224impl COUNTRST_R {
225    ///Get enumerated values variant
226    #[inline(always)]
227    pub const fn variant(&self) -> COUNTRSTR {
228        match self.bits {
229            false => COUNTRSTR::Idle,
230            true => COUNTRSTR::Busy,
231        }
232    }
233    ///Triggering of reset is possible
234    #[inline(always)]
235    pub fn is_idle(&self) -> bool {
236        *self == COUNTRSTR::Idle
237    }
238    ///Reset in progress, do not write 1 to this field
239    #[inline(always)]
240    pub fn is_busy(&self) -> bool {
241        *self == COUNTRSTR::Busy
242    }
243}
244/**Counter reset
245
246Value on reset: 0*/
247#[cfg_attr(feature = "defmt", derive(defmt::Format))]
248#[derive(Clone, Copy, Debug, PartialEq, Eq)]
249pub enum COUNTRSTW {
250    ///1: Trigger synchronous reset of CNT (3 LPTimer core clock cycles)
251    Reset = 1,
252}
253impl From<COUNTRSTW> for bool {
254    #[inline(always)]
255    fn from(variant: COUNTRSTW) -> Self {
256        variant as u8 != 0
257    }
258}
259///Field `COUNTRST` writer - Counter reset
260pub type COUNTRST_W<'a, REG> = crate::BitWriter<'a, REG, COUNTRSTW>;
261impl<'a, REG> COUNTRST_W<'a, REG>
262where
263    REG: crate::Writable + crate::RegisterSpec,
264{
265    ///Trigger synchronous reset of CNT (3 LPTimer core clock cycles)
266    #[inline(always)]
267    pub fn reset(self) -> &'a mut crate::W<REG> {
268        self.variant(COUNTRSTW::Reset)
269    }
270}
271impl R {
272    ///Bit 0 - LPTIM Enable
273    #[inline(always)]
274    pub fn enable(&self) -> ENABLE_R {
275        ENABLE_R::new((self.bits & 1) != 0)
276    }
277    ///Bit 1 - LPTIM start in single mode
278    #[inline(always)]
279    pub fn sngstrt(&self) -> SNGSTRT_R {
280        SNGSTRT_R::new(((self.bits >> 1) & 1) != 0)
281    }
282    ///Bit 2 - Timer start in continuous mode
283    #[inline(always)]
284    pub fn cntstrt(&self) -> CNTSTRT_R {
285        CNTSTRT_R::new(((self.bits >> 2) & 1) != 0)
286    }
287    ///Bit 3 - Reset after read enable
288    #[inline(always)]
289    pub fn rstare(&self) -> RSTARE_R {
290        RSTARE_R::new(((self.bits >> 3) & 1) != 0)
291    }
292    ///Bit 4 - Counter reset
293    #[inline(always)]
294    pub fn countrst(&self) -> COUNTRST_R {
295        COUNTRST_R::new(((self.bits >> 4) & 1) != 0)
296    }
297}
298impl core::fmt::Debug for R {
299    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
300        f.debug_struct("CR")
301            .field("cntstrt", &self.cntstrt())
302            .field("sngstrt", &self.sngstrt())
303            .field("enable", &self.enable())
304            .field("countrst", &self.countrst())
305            .field("rstare", &self.rstare())
306            .finish()
307    }
308}
309impl W {
310    ///Bit 0 - LPTIM Enable
311    #[inline(always)]
312    pub fn enable(&mut self) -> ENABLE_W<CRrs> {
313        ENABLE_W::new(self, 0)
314    }
315    ///Bit 1 - LPTIM start in single mode
316    #[inline(always)]
317    pub fn sngstrt(&mut self) -> SNGSTRT_W<CRrs> {
318        SNGSTRT_W::new(self, 1)
319    }
320    ///Bit 2 - Timer start in continuous mode
321    #[inline(always)]
322    pub fn cntstrt(&mut self) -> CNTSTRT_W<CRrs> {
323        CNTSTRT_W::new(self, 2)
324    }
325    ///Bit 3 - Reset after read enable
326    #[inline(always)]
327    pub fn rstare(&mut self) -> RSTARE_W<CRrs> {
328        RSTARE_W::new(self, 3)
329    }
330    ///Bit 4 - Counter reset
331    #[inline(always)]
332    pub fn countrst(&mut self) -> COUNTRST_W<CRrs> {
333        COUNTRST_W::new(self, 4)
334    }
335}
336/**Control Register
337
338You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
339
340See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L562.html#LPTIM1:CR)*/
341pub struct CRrs;
342impl crate::RegisterSpec for CRrs {
343    type Ux = u32;
344}
345///`read()` method returns [`cr::R`](R) reader structure
346impl crate::Readable for CRrs {}
347///`write(|w| ..)` method takes [`cr::W`](W) writer structure
348impl crate::Writable for CRrs {
349    type Safety = crate::Unsafe;
350}
351///`reset()` method sets CR to value 0
352impl crate::Resettable for CRrs {}
stm32l5/stm32l562/lptim1/cr.rs

stm32l5/stm32l562/lptim1/
cr.rs
