stm32l5/stm32l562/lptim1/
cfgr.rs

1///Register `CFGR` reader
2pub type R = crate::R<CFGRrs>;
3///Register `CFGR` writer
4pub type W = crate::W<CFGRrs>;
5/**Clock selector
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CKSEL {
11    ///0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
12    Internal = 0,
13    ///1: LPTIM is clocked by an external clock source through the LPTIM external Input1
14    External = 1,
15}
16impl From<CKSEL> for bool {
17    #[inline(always)]
18    fn from(variant: CKSEL) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CKSEL` reader - Clock selector
23pub type CKSEL_R = crate::BitReader<CKSEL>;
24impl CKSEL_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CKSEL {
28        match self.bits {
29            false => CKSEL::Internal,
30            true => CKSEL::External,
31        }
32    }
33    ///LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
34    #[inline(always)]
35    pub fn is_internal(&self) -> bool {
36        *self == CKSEL::Internal
37    }
38    ///LPTIM is clocked by an external clock source through the LPTIM external Input1
39    #[inline(always)]
40    pub fn is_external(&self) -> bool {
41        *self == CKSEL::External
42    }
43}
44///Field `CKSEL` writer - Clock selector
45pub type CKSEL_W<'a, REG> = crate::BitWriter<'a, REG, CKSEL>;
46impl<'a, REG> CKSEL_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
51    #[inline(always)]
52    pub fn internal(self) -> &'a mut crate::W<REG> {
53        self.variant(CKSEL::Internal)
54    }
55    ///LPTIM is clocked by an external clock source through the LPTIM external Input1
56    #[inline(always)]
57    pub fn external(self) -> &'a mut crate::W<REG> {
58        self.variant(CKSEL::External)
59    }
60}
61/**Clock Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum CKPOL {
68    ///0: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
69    RisingEdge = 0,
70    ///1: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
71    FallingEdge = 1,
72    ///2: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.
73    BothEdges = 2,
74}
75impl From<CKPOL> for u8 {
76    #[inline(always)]
77    fn from(variant: CKPOL) -> Self {
78        variant as _
79    }
80}
81impl crate::FieldSpec for CKPOL {
82    type Ux = u8;
83}
84impl crate::IsEnum for CKPOL {}
85///Field `CKPOL` reader - Clock Polarity
86pub type CKPOL_R = crate::FieldReader<CKPOL>;
87impl CKPOL_R {
88    ///Get enumerated values variant
89    #[inline(always)]
90    pub const fn variant(&self) -> Option<CKPOL> {
91        match self.bits {
92            0 => Some(CKPOL::RisingEdge),
93            1 => Some(CKPOL::FallingEdge),
94            2 => Some(CKPOL::BothEdges),
95            _ => None,
96        }
97    }
98    ///The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
99    #[inline(always)]
100    pub fn is_rising_edge(&self) -> bool {
101        *self == CKPOL::RisingEdge
102    }
103    ///The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
104    #[inline(always)]
105    pub fn is_falling_edge(&self) -> bool {
106        *self == CKPOL::FallingEdge
107    }
108    ///Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.
109    #[inline(always)]
110    pub fn is_both_edges(&self) -> bool {
111        *self == CKPOL::BothEdges
112    }
113}
114///Field `CKPOL` writer - Clock Polarity
115pub type CKPOL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CKPOL>;
116impl<'a, REG> CKPOL_W<'a, REG>
117where
118    REG: crate::Writable + crate::RegisterSpec,
119    REG::Ux: From<u8>,
120{
121    ///The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
122    #[inline(always)]
123    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
124        self.variant(CKPOL::RisingEdge)
125    }
126    ///The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
127    #[inline(always)]
128    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
129        self.variant(CKPOL::FallingEdge)
130    }
131    ///Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.
132    #[inline(always)]
133    pub fn both_edges(self) -> &'a mut crate::W<REG> {
134        self.variant(CKPOL::BothEdges)
135    }
136}
137/**Configurable digital filter for external clock
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142#[repr(u8)]
143pub enum CKFLT {
144    ///0: Any external clock signal level change is considered as a valid transition
145    Immediate = 0,
146    ///1: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
147    Clocks2 = 1,
148    ///2: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
149    Clocks4 = 2,
150    ///3: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition
151    Clocks8 = 3,
152}
153impl From<CKFLT> for u8 {
154    #[inline(always)]
155    fn from(variant: CKFLT) -> Self {
156        variant as _
157    }
158}
159impl crate::FieldSpec for CKFLT {
160    type Ux = u8;
161}
162impl crate::IsEnum for CKFLT {}
163///Field `CKFLT` reader - Configurable digital filter for external clock
164pub type CKFLT_R = crate::FieldReader<CKFLT>;
165impl CKFLT_R {
166    ///Get enumerated values variant
167    #[inline(always)]
168    pub const fn variant(&self) -> CKFLT {
169        match self.bits {
170            0 => CKFLT::Immediate,
171            1 => CKFLT::Clocks2,
172            2 => CKFLT::Clocks4,
173            3 => CKFLT::Clocks8,
174            _ => unreachable!(),
175        }
176    }
177    ///Any external clock signal level change is considered as a valid transition
178    #[inline(always)]
179    pub fn is_immediate(&self) -> bool {
180        *self == CKFLT::Immediate
181    }
182    ///External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
183    #[inline(always)]
184    pub fn is_clocks2(&self) -> bool {
185        *self == CKFLT::Clocks2
186    }
187    ///External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
188    #[inline(always)]
189    pub fn is_clocks4(&self) -> bool {
190        *self == CKFLT::Clocks4
191    }
192    ///External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition
193    #[inline(always)]
194    pub fn is_clocks8(&self) -> bool {
195        *self == CKFLT::Clocks8
196    }
197}
198///Field `CKFLT` writer - Configurable digital filter for external clock
199pub type CKFLT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CKFLT, crate::Safe>;
200impl<'a, REG> CKFLT_W<'a, REG>
201where
202    REG: crate::Writable + crate::RegisterSpec,
203    REG::Ux: From<u8>,
204{
205    ///Any external clock signal level change is considered as a valid transition
206    #[inline(always)]
207    pub fn immediate(self) -> &'a mut crate::W<REG> {
208        self.variant(CKFLT::Immediate)
209    }
210    ///External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
211    #[inline(always)]
212    pub fn clocks2(self) -> &'a mut crate::W<REG> {
213        self.variant(CKFLT::Clocks2)
214    }
215    ///External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
216    #[inline(always)]
217    pub fn clocks4(self) -> &'a mut crate::W<REG> {
218        self.variant(CKFLT::Clocks4)
219    }
220    ///External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition
221    #[inline(always)]
222    pub fn clocks8(self) -> &'a mut crate::W<REG> {
223        self.variant(CKFLT::Clocks8)
224    }
225}
226/**Configurable digital filter for trigger
227
228Value on reset: 0*/
229#[cfg_attr(feature = "defmt", derive(defmt::Format))]
230#[derive(Clone, Copy, Debug, PartialEq, Eq)]
231#[repr(u8)]
232pub enum TRGFLT {
233    ///0: Any trigger active level change is considered as a valid trigger
234    Immediate = 0,
235    ///1: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
236    Clocks2 = 1,
237    ///2: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
238    Clocks4 = 2,
239    ///3: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger
240    Clocks8 = 3,
241}
242impl From<TRGFLT> for u8 {
243    #[inline(always)]
244    fn from(variant: TRGFLT) -> Self {
245        variant as _
246    }
247}
248impl crate::FieldSpec for TRGFLT {
249    type Ux = u8;
250}
251impl crate::IsEnum for TRGFLT {}
252///Field `TRGFLT` reader - Configurable digital filter for trigger
253pub type TRGFLT_R = crate::FieldReader<TRGFLT>;
254impl TRGFLT_R {
255    ///Get enumerated values variant
256    #[inline(always)]
257    pub const fn variant(&self) -> TRGFLT {
258        match self.bits {
259            0 => TRGFLT::Immediate,
260            1 => TRGFLT::Clocks2,
261            2 => TRGFLT::Clocks4,
262            3 => TRGFLT::Clocks8,
263            _ => unreachable!(),
264        }
265    }
266    ///Any trigger active level change is considered as a valid trigger
267    #[inline(always)]
268    pub fn is_immediate(&self) -> bool {
269        *self == TRGFLT::Immediate
270    }
271    ///Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
272    #[inline(always)]
273    pub fn is_clocks2(&self) -> bool {
274        *self == TRGFLT::Clocks2
275    }
276    ///Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
277    #[inline(always)]
278    pub fn is_clocks4(&self) -> bool {
279        *self == TRGFLT::Clocks4
280    }
281    ///Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger
282    #[inline(always)]
283    pub fn is_clocks8(&self) -> bool {
284        *self == TRGFLT::Clocks8
285    }
286}
287///Field `TRGFLT` writer - Configurable digital filter for trigger
288pub type TRGFLT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TRGFLT, crate::Safe>;
289impl<'a, REG> TRGFLT_W<'a, REG>
290where
291    REG: crate::Writable + crate::RegisterSpec,
292    REG::Ux: From<u8>,
293{
294    ///Any trigger active level change is considered as a valid trigger
295    #[inline(always)]
296    pub fn immediate(self) -> &'a mut crate::W<REG> {
297        self.variant(TRGFLT::Immediate)
298    }
299    ///Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
300    #[inline(always)]
301    pub fn clocks2(self) -> &'a mut crate::W<REG> {
302        self.variant(TRGFLT::Clocks2)
303    }
304    ///Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
305    #[inline(always)]
306    pub fn clocks4(self) -> &'a mut crate::W<REG> {
307        self.variant(TRGFLT::Clocks4)
308    }
309    ///Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger
310    #[inline(always)]
311    pub fn clocks8(self) -> &'a mut crate::W<REG> {
312        self.variant(TRGFLT::Clocks8)
313    }
314}
315/**Clock prescaler
316
317Value on reset: 0*/
318#[cfg_attr(feature = "defmt", derive(defmt::Format))]
319#[derive(Clone, Copy, Debug, PartialEq, Eq)]
320#[repr(u8)]
321pub enum PRESC {
322    ///0: /1
323    Div1 = 0,
324    ///1: /2
325    Div2 = 1,
326    ///2: /4
327    Div4 = 2,
328    ///3: /8
329    Div8 = 3,
330    ///4: /16
331    Div16 = 4,
332    ///5: /32
333    Div32 = 5,
334    ///6: /64
335    Div64 = 6,
336    ///7: /128
337    Div128 = 7,
338}
339impl From<PRESC> for u8 {
340    #[inline(always)]
341    fn from(variant: PRESC) -> Self {
342        variant as _
343    }
344}
345impl crate::FieldSpec for PRESC {
346    type Ux = u8;
347}
348impl crate::IsEnum for PRESC {}
349///Field `PRESC` reader - Clock prescaler
350pub type PRESC_R = crate::FieldReader<PRESC>;
351impl PRESC_R {
352    ///Get enumerated values variant
353    #[inline(always)]
354    pub const fn variant(&self) -> PRESC {
355        match self.bits {
356            0 => PRESC::Div1,
357            1 => PRESC::Div2,
358            2 => PRESC::Div4,
359            3 => PRESC::Div8,
360            4 => PRESC::Div16,
361            5 => PRESC::Div32,
362            6 => PRESC::Div64,
363            7 => PRESC::Div128,
364            _ => unreachable!(),
365        }
366    }
367    #[doc = "/1"]
368    #[inline(always)]
369    pub fn is_div1(&self) -> bool {
370        *self == PRESC::Div1
371    }
372    #[doc = "/2"]
373    #[inline(always)]
374    pub fn is_div2(&self) -> bool {
375        *self == PRESC::Div2
376    }
377    #[doc = "/4"]
378    #[inline(always)]
379    pub fn is_div4(&self) -> bool {
380        *self == PRESC::Div4
381    }
382    #[doc = "/8"]
383    #[inline(always)]
384    pub fn is_div8(&self) -> bool {
385        *self == PRESC::Div8
386    }
387    #[doc = "/16"]
388    #[inline(always)]
389    pub fn is_div16(&self) -> bool {
390        *self == PRESC::Div16
391    }
392    #[doc = "/32"]
393    #[inline(always)]
394    pub fn is_div32(&self) -> bool {
395        *self == PRESC::Div32
396    }
397    #[doc = "/64"]
398    #[inline(always)]
399    pub fn is_div64(&self) -> bool {
400        *self == PRESC::Div64
401    }
402    #[doc = "/128"]
403    #[inline(always)]
404    pub fn is_div128(&self) -> bool {
405        *self == PRESC::Div128
406    }
407}
408///Field `PRESC` writer - Clock prescaler
409pub type PRESC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PRESC, crate::Safe>;
410impl<'a, REG> PRESC_W<'a, REG>
411where
412    REG: crate::Writable + crate::RegisterSpec,
413    REG::Ux: From<u8>,
414{
415    #[doc = "/1"]
416    #[inline(always)]
417    pub fn div1(self) -> &'a mut crate::W<REG> {
418        self.variant(PRESC::Div1)
419    }
420    #[doc = "/2"]
421    #[inline(always)]
422    pub fn div2(self) -> &'a mut crate::W<REG> {
423        self.variant(PRESC::Div2)
424    }
425    #[doc = "/4"]
426    #[inline(always)]
427    pub fn div4(self) -> &'a mut crate::W<REG> {
428        self.variant(PRESC::Div4)
429    }
430    #[doc = "/8"]
431    #[inline(always)]
432    pub fn div8(self) -> &'a mut crate::W<REG> {
433        self.variant(PRESC::Div8)
434    }
435    #[doc = "/16"]
436    #[inline(always)]
437    pub fn div16(self) -> &'a mut crate::W<REG> {
438        self.variant(PRESC::Div16)
439    }
440    #[doc = "/32"]
441    #[inline(always)]
442    pub fn div32(self) -> &'a mut crate::W<REG> {
443        self.variant(PRESC::Div32)
444    }
445    #[doc = "/64"]
446    #[inline(always)]
447    pub fn div64(self) -> &'a mut crate::W<REG> {
448        self.variant(PRESC::Div64)
449    }
450    #[doc = "/128"]
451    #[inline(always)]
452    pub fn div128(self) -> &'a mut crate::W<REG> {
453        self.variant(PRESC::Div128)
454    }
455}
456/**Trigger selector
457
458Value on reset: 0*/
459#[cfg_attr(feature = "defmt", derive(defmt::Format))]
460#[derive(Clone, Copy, Debug, PartialEq, Eq)]
461#[repr(u8)]
462pub enum TRIGSEL {
463    ///0: lptim_ext_trig0
464    Trig0 = 0,
465    ///1: lptim_ext_trig1
466    Trig1 = 1,
467    ///2: lptim_ext_trig2
468    Trig2 = 2,
469    ///3: lptim_ext_trig3
470    Trig3 = 3,
471    ///4: lptim_ext_trig4
472    Trig4 = 4,
473    ///5: lptim_ext_trig5
474    Trig5 = 5,
475    ///6: lptim_ext_trig6
476    Trig6 = 6,
477    ///7: lptim_ext_trig7
478    Trig7 = 7,
479}
480impl From<TRIGSEL> for u8 {
481    #[inline(always)]
482    fn from(variant: TRIGSEL) -> Self {
483        variant as _
484    }
485}
486impl crate::FieldSpec for TRIGSEL {
487    type Ux = u8;
488}
489impl crate::IsEnum for TRIGSEL {}
490///Field `TRIGSEL` reader - Trigger selector
491pub type TRIGSEL_R = crate::FieldReader<TRIGSEL>;
492impl TRIGSEL_R {
493    ///Get enumerated values variant
494    #[inline(always)]
495    pub const fn variant(&self) -> TRIGSEL {
496        match self.bits {
497            0 => TRIGSEL::Trig0,
498            1 => TRIGSEL::Trig1,
499            2 => TRIGSEL::Trig2,
500            3 => TRIGSEL::Trig3,
501            4 => TRIGSEL::Trig4,
502            5 => TRIGSEL::Trig5,
503            6 => TRIGSEL::Trig6,
504            7 => TRIGSEL::Trig7,
505            _ => unreachable!(),
506        }
507    }
508    ///lptim_ext_trig0
509    #[inline(always)]
510    pub fn is_trig0(&self) -> bool {
511        *self == TRIGSEL::Trig0
512    }
513    ///lptim_ext_trig1
514    #[inline(always)]
515    pub fn is_trig1(&self) -> bool {
516        *self == TRIGSEL::Trig1
517    }
518    ///lptim_ext_trig2
519    #[inline(always)]
520    pub fn is_trig2(&self) -> bool {
521        *self == TRIGSEL::Trig2
522    }
523    ///lptim_ext_trig3
524    #[inline(always)]
525    pub fn is_trig3(&self) -> bool {
526        *self == TRIGSEL::Trig3
527    }
528    ///lptim_ext_trig4
529    #[inline(always)]
530    pub fn is_trig4(&self) -> bool {
531        *self == TRIGSEL::Trig4
532    }
533    ///lptim_ext_trig5
534    #[inline(always)]
535    pub fn is_trig5(&self) -> bool {
536        *self == TRIGSEL::Trig5
537    }
538    ///lptim_ext_trig6
539    #[inline(always)]
540    pub fn is_trig6(&self) -> bool {
541        *self == TRIGSEL::Trig6
542    }
543    ///lptim_ext_trig7
544    #[inline(always)]
545    pub fn is_trig7(&self) -> bool {
546        *self == TRIGSEL::Trig7
547    }
548}
549///Field `TRIGSEL` writer - Trigger selector
550pub type TRIGSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TRIGSEL, crate::Safe>;
551impl<'a, REG> TRIGSEL_W<'a, REG>
552where
553    REG: crate::Writable + crate::RegisterSpec,
554    REG::Ux: From<u8>,
555{
556    ///lptim_ext_trig0
557    #[inline(always)]
558    pub fn trig0(self) -> &'a mut crate::W<REG> {
559        self.variant(TRIGSEL::Trig0)
560    }
561    ///lptim_ext_trig1
562    #[inline(always)]
563    pub fn trig1(self) -> &'a mut crate::W<REG> {
564        self.variant(TRIGSEL::Trig1)
565    }
566    ///lptim_ext_trig2
567    #[inline(always)]
568    pub fn trig2(self) -> &'a mut crate::W<REG> {
569        self.variant(TRIGSEL::Trig2)
570    }
571    ///lptim_ext_trig3
572    #[inline(always)]
573    pub fn trig3(self) -> &'a mut crate::W<REG> {
574        self.variant(TRIGSEL::Trig3)
575    }
576    ///lptim_ext_trig4
577    #[inline(always)]
578    pub fn trig4(self) -> &'a mut crate::W<REG> {
579        self.variant(TRIGSEL::Trig4)
580    }
581    ///lptim_ext_trig5
582    #[inline(always)]
583    pub fn trig5(self) -> &'a mut crate::W<REG> {
584        self.variant(TRIGSEL::Trig5)
585    }
586    ///lptim_ext_trig6
587    #[inline(always)]
588    pub fn trig6(self) -> &'a mut crate::W<REG> {
589        self.variant(TRIGSEL::Trig6)
590    }
591    ///lptim_ext_trig7
592    #[inline(always)]
593    pub fn trig7(self) -> &'a mut crate::W<REG> {
594        self.variant(TRIGSEL::Trig7)
595    }
596}
597/**Trigger enable and polarity
598
599Value on reset: 0*/
600#[cfg_attr(feature = "defmt", derive(defmt::Format))]
601#[derive(Clone, Copy, Debug, PartialEq, Eq)]
602#[repr(u8)]
603pub enum TRIGEN {
604    ///0: Software trigger (counting start is initiated by software)
605    Sw = 0,
606    ///1: Rising edge is the active edge
607    RisingEdge = 1,
608    ///2: Falling edge is the active edge
609    FallingEdge = 2,
610    ///3: Both edges are active edges
611    BothEdges = 3,
612}
613impl From<TRIGEN> for u8 {
614    #[inline(always)]
615    fn from(variant: TRIGEN) -> Self {
616        variant as _
617    }
618}
619impl crate::FieldSpec for TRIGEN {
620    type Ux = u8;
621}
622impl crate::IsEnum for TRIGEN {}
623///Field `TRIGEN` reader - Trigger enable and polarity
624pub type TRIGEN_R = crate::FieldReader<TRIGEN>;
625impl TRIGEN_R {
626    ///Get enumerated values variant
627    #[inline(always)]
628    pub const fn variant(&self) -> TRIGEN {
629        match self.bits {
630            0 => TRIGEN::Sw,
631            1 => TRIGEN::RisingEdge,
632            2 => TRIGEN::FallingEdge,
633            3 => TRIGEN::BothEdges,
634            _ => unreachable!(),
635        }
636    }
637    ///Software trigger (counting start is initiated by software)
638    #[inline(always)]
639    pub fn is_sw(&self) -> bool {
640        *self == TRIGEN::Sw
641    }
642    ///Rising edge is the active edge
643    #[inline(always)]
644    pub fn is_rising_edge(&self) -> bool {
645        *self == TRIGEN::RisingEdge
646    }
647    ///Falling edge is the active edge
648    #[inline(always)]
649    pub fn is_falling_edge(&self) -> bool {
650        *self == TRIGEN::FallingEdge
651    }
652    ///Both edges are active edges
653    #[inline(always)]
654    pub fn is_both_edges(&self) -> bool {
655        *self == TRIGEN::BothEdges
656    }
657}
658///Field `TRIGEN` writer - Trigger enable and polarity
659pub type TRIGEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TRIGEN, crate::Safe>;
660impl<'a, REG> TRIGEN_W<'a, REG>
661where
662    REG: crate::Writable + crate::RegisterSpec,
663    REG::Ux: From<u8>,
664{
665    ///Software trigger (counting start is initiated by software)
666    #[inline(always)]
667    pub fn sw(self) -> &'a mut crate::W<REG> {
668        self.variant(TRIGEN::Sw)
669    }
670    ///Rising edge is the active edge
671    #[inline(always)]
672    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
673        self.variant(TRIGEN::RisingEdge)
674    }
675    ///Falling edge is the active edge
676    #[inline(always)]
677    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
678        self.variant(TRIGEN::FallingEdge)
679    }
680    ///Both edges are active edges
681    #[inline(always)]
682    pub fn both_edges(self) -> &'a mut crate::W<REG> {
683        self.variant(TRIGEN::BothEdges)
684    }
685}
686/**Timeout enable
687
688Value on reset: 0*/
689#[cfg_attr(feature = "defmt", derive(defmt::Format))]
690#[derive(Clone, Copy, Debug, PartialEq, Eq)]
691pub enum TIMOUT {
692    ///0: A trigger event arriving when the timer is already started will be ignored
693    Disabled = 0,
694    ///1: A trigger event arriving when the timer is already started will reset and restart the counter
695    Enabled = 1,
696}
697impl From<TIMOUT> for bool {
698    #[inline(always)]
699    fn from(variant: TIMOUT) -> Self {
700        variant as u8 != 0
701    }
702}
703///Field `TIMOUT` reader - Timeout enable
704pub type TIMOUT_R = crate::BitReader<TIMOUT>;
705impl TIMOUT_R {
706    ///Get enumerated values variant
707    #[inline(always)]
708    pub const fn variant(&self) -> TIMOUT {
709        match self.bits {
710            false => TIMOUT::Disabled,
711            true => TIMOUT::Enabled,
712        }
713    }
714    ///A trigger event arriving when the timer is already started will be ignored
715    #[inline(always)]
716    pub fn is_disabled(&self) -> bool {
717        *self == TIMOUT::Disabled
718    }
719    ///A trigger event arriving when the timer is already started will reset and restart the counter
720    #[inline(always)]
721    pub fn is_enabled(&self) -> bool {
722        *self == TIMOUT::Enabled
723    }
724}
725///Field `TIMOUT` writer - Timeout enable
726pub type TIMOUT_W<'a, REG> = crate::BitWriter<'a, REG, TIMOUT>;
727impl<'a, REG> TIMOUT_W<'a, REG>
728where
729    REG: crate::Writable + crate::RegisterSpec,
730{
731    ///A trigger event arriving when the timer is already started will be ignored
732    #[inline(always)]
733    pub fn disabled(self) -> &'a mut crate::W<REG> {
734        self.variant(TIMOUT::Disabled)
735    }
736    ///A trigger event arriving when the timer is already started will reset and restart the counter
737    #[inline(always)]
738    pub fn enabled(self) -> &'a mut crate::W<REG> {
739        self.variant(TIMOUT::Enabled)
740    }
741}
742/**Waveform shape
743
744Value on reset: 0*/
745#[cfg_attr(feature = "defmt", derive(defmt::Format))]
746#[derive(Clone, Copy, Debug, PartialEq, Eq)]
747pub enum WAVE {
748    ///0: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
749    Inactive = 0,
750    ///1: Activate the Set-once mode
751    Active = 1,
752}
753impl From<WAVE> for bool {
754    #[inline(always)]
755    fn from(variant: WAVE) -> Self {
756        variant as u8 != 0
757    }
758}
759///Field `WAVE` reader - Waveform shape
760pub type WAVE_R = crate::BitReader<WAVE>;
761impl WAVE_R {
762    ///Get enumerated values variant
763    #[inline(always)]
764    pub const fn variant(&self) -> WAVE {
765        match self.bits {
766            false => WAVE::Inactive,
767            true => WAVE::Active,
768        }
769    }
770    ///Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
771    #[inline(always)]
772    pub fn is_inactive(&self) -> bool {
773        *self == WAVE::Inactive
774    }
775    ///Activate the Set-once mode
776    #[inline(always)]
777    pub fn is_active(&self) -> bool {
778        *self == WAVE::Active
779    }
780}
781///Field `WAVE` writer - Waveform shape
782pub type WAVE_W<'a, REG> = crate::BitWriter<'a, REG, WAVE>;
783impl<'a, REG> WAVE_W<'a, REG>
784where
785    REG: crate::Writable + crate::RegisterSpec,
786{
787    ///Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
788    #[inline(always)]
789    pub fn inactive(self) -> &'a mut crate::W<REG> {
790        self.variant(WAVE::Inactive)
791    }
792    ///Activate the Set-once mode
793    #[inline(always)]
794    pub fn active(self) -> &'a mut crate::W<REG> {
795        self.variant(WAVE::Active)
796    }
797}
798/**Waveform shape polarity
799
800Value on reset: 0*/
801#[cfg_attr(feature = "defmt", derive(defmt::Format))]
802#[derive(Clone, Copy, Debug, PartialEq, Eq)]
803pub enum WAVPOL {
804    ///0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
805    Positive = 0,
806    ///1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers
807    Negative = 1,
808}
809impl From<WAVPOL> for bool {
810    #[inline(always)]
811    fn from(variant: WAVPOL) -> Self {
812        variant as u8 != 0
813    }
814}
815///Field `WAVPOL` reader - Waveform shape polarity
816pub type WAVPOL_R = crate::BitReader<WAVPOL>;
817impl WAVPOL_R {
818    ///Get enumerated values variant
819    #[inline(always)]
820    pub const fn variant(&self) -> WAVPOL {
821        match self.bits {
822            false => WAVPOL::Positive,
823            true => WAVPOL::Negative,
824        }
825    }
826    ///The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
827    #[inline(always)]
828    pub fn is_positive(&self) -> bool {
829        *self == WAVPOL::Positive
830    }
831    ///The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers
832    #[inline(always)]
833    pub fn is_negative(&self) -> bool {
834        *self == WAVPOL::Negative
835    }
836}
837///Field `WAVPOL` writer - Waveform shape polarity
838pub type WAVPOL_W<'a, REG> = crate::BitWriter<'a, REG, WAVPOL>;
839impl<'a, REG> WAVPOL_W<'a, REG>
840where
841    REG: crate::Writable + crate::RegisterSpec,
842{
843    ///The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
844    #[inline(always)]
845    pub fn positive(self) -> &'a mut crate::W<REG> {
846        self.variant(WAVPOL::Positive)
847    }
848    ///The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers
849    #[inline(always)]
850    pub fn negative(self) -> &'a mut crate::W<REG> {
851        self.variant(WAVPOL::Negative)
852    }
853}
854/**Registers update mode
855
856Value on reset: 0*/
857#[cfg_attr(feature = "defmt", derive(defmt::Format))]
858#[derive(Clone, Copy, Debug, PartialEq, Eq)]
859pub enum PRELOAD {
860    ///0: Registers are updated after each APB bus write access
861    Immediate = 0,
862    ///1: Registers are updated at the end of the current LPTIM period
863    EndOfPeriod = 1,
864}
865impl From<PRELOAD> for bool {
866    #[inline(always)]
867    fn from(variant: PRELOAD) -> Self {
868        variant as u8 != 0
869    }
870}
871///Field `PRELOAD` reader - Registers update mode
872pub type PRELOAD_R = crate::BitReader<PRELOAD>;
873impl PRELOAD_R {
874    ///Get enumerated values variant
875    #[inline(always)]
876    pub const fn variant(&self) -> PRELOAD {
877        match self.bits {
878            false => PRELOAD::Immediate,
879            true => PRELOAD::EndOfPeriod,
880        }
881    }
882    ///Registers are updated after each APB bus write access
883    #[inline(always)]
884    pub fn is_immediate(&self) -> bool {
885        *self == PRELOAD::Immediate
886    }
887    ///Registers are updated at the end of the current LPTIM period
888    #[inline(always)]
889    pub fn is_end_of_period(&self) -> bool {
890        *self == PRELOAD::EndOfPeriod
891    }
892}
893///Field `PRELOAD` writer - Registers update mode
894pub type PRELOAD_W<'a, REG> = crate::BitWriter<'a, REG, PRELOAD>;
895impl<'a, REG> PRELOAD_W<'a, REG>
896where
897    REG: crate::Writable + crate::RegisterSpec,
898{
899    ///Registers are updated after each APB bus write access
900    #[inline(always)]
901    pub fn immediate(self) -> &'a mut crate::W<REG> {
902        self.variant(PRELOAD::Immediate)
903    }
904    ///Registers are updated at the end of the current LPTIM period
905    #[inline(always)]
906    pub fn end_of_period(self) -> &'a mut crate::W<REG> {
907        self.variant(PRELOAD::EndOfPeriod)
908    }
909}
910/**counter mode enabled
911
912Value on reset: 0*/
913#[cfg_attr(feature = "defmt", derive(defmt::Format))]
914#[derive(Clone, Copy, Debug, PartialEq, Eq)]
915pub enum COUNTMODE {
916    ///0: The counter is incremented following each internal clock pulse
917    Internal = 0,
918    ///1: The counter is incremented following each valid clock pulse on the LPTIM external Input1
919    External = 1,
920}
921impl From<COUNTMODE> for bool {
922    #[inline(always)]
923    fn from(variant: COUNTMODE) -> Self {
924        variant as u8 != 0
925    }
926}
927///Field `COUNTMODE` reader - counter mode enabled
928pub type COUNTMODE_R = crate::BitReader<COUNTMODE>;
929impl COUNTMODE_R {
930    ///Get enumerated values variant
931    #[inline(always)]
932    pub const fn variant(&self) -> COUNTMODE {
933        match self.bits {
934            false => COUNTMODE::Internal,
935            true => COUNTMODE::External,
936        }
937    }
938    ///The counter is incremented following each internal clock pulse
939    #[inline(always)]
940    pub fn is_internal(&self) -> bool {
941        *self == COUNTMODE::Internal
942    }
943    ///The counter is incremented following each valid clock pulse on the LPTIM external Input1
944    #[inline(always)]
945    pub fn is_external(&self) -> bool {
946        *self == COUNTMODE::External
947    }
948}
949///Field `COUNTMODE` writer - counter mode enabled
950pub type COUNTMODE_W<'a, REG> = crate::BitWriter<'a, REG, COUNTMODE>;
951impl<'a, REG> COUNTMODE_W<'a, REG>
952where
953    REG: crate::Writable + crate::RegisterSpec,
954{
955    ///The counter is incremented following each internal clock pulse
956    #[inline(always)]
957    pub fn internal(self) -> &'a mut crate::W<REG> {
958        self.variant(COUNTMODE::Internal)
959    }
960    ///The counter is incremented following each valid clock pulse on the LPTIM external Input1
961    #[inline(always)]
962    pub fn external(self) -> &'a mut crate::W<REG> {
963        self.variant(COUNTMODE::External)
964    }
965}
966/**Encoder mode enable
967
968Value on reset: 0*/
969#[cfg_attr(feature = "defmt", derive(defmt::Format))]
970#[derive(Clone, Copy, Debug, PartialEq, Eq)]
971pub enum ENC {
972    ///0: Encoder mode disabled
973    Disabled = 0,
974    ///1: Encoder mode enabled
975    Enabled = 1,
976}
977impl From<ENC> for bool {
978    #[inline(always)]
979    fn from(variant: ENC) -> Self {
980        variant as u8 != 0
981    }
982}
983///Field `ENC` reader - Encoder mode enable
984pub type ENC_R = crate::BitReader<ENC>;
985impl ENC_R {
986    ///Get enumerated values variant
987    #[inline(always)]
988    pub const fn variant(&self) -> ENC {
989        match self.bits {
990            false => ENC::Disabled,
991            true => ENC::Enabled,
992        }
993    }
994    ///Encoder mode disabled
995    #[inline(always)]
996    pub fn is_disabled(&self) -> bool {
997        *self == ENC::Disabled
998    }
999    ///Encoder mode enabled
1000    #[inline(always)]
1001    pub fn is_enabled(&self) -> bool {
1002        *self == ENC::Enabled
1003    }
1004}
1005///Field `ENC` writer - Encoder mode enable
1006pub type ENC_W<'a, REG> = crate::BitWriter<'a, REG, ENC>;
1007impl<'a, REG> ENC_W<'a, REG>
1008where
1009    REG: crate::Writable + crate::RegisterSpec,
1010{
1011    ///Encoder mode disabled
1012    #[inline(always)]
1013    pub fn disabled(self) -> &'a mut crate::W<REG> {
1014        self.variant(ENC::Disabled)
1015    }
1016    ///Encoder mode enabled
1017    #[inline(always)]
1018    pub fn enabled(self) -> &'a mut crate::W<REG> {
1019        self.variant(ENC::Enabled)
1020    }
1021}
1022impl R {
1023    ///Bit 0 - Clock selector
1024    #[inline(always)]
1025    pub fn cksel(&self) -> CKSEL_R {
1026        CKSEL_R::new((self.bits & 1) != 0)
1027    }
1028    ///Bits 1:2 - Clock Polarity
1029    #[inline(always)]
1030    pub fn ckpol(&self) -> CKPOL_R {
1031        CKPOL_R::new(((self.bits >> 1) & 3) as u8)
1032    }
1033    ///Bits 3:4 - Configurable digital filter for external clock
1034    #[inline(always)]
1035    pub fn ckflt(&self) -> CKFLT_R {
1036        CKFLT_R::new(((self.bits >> 3) & 3) as u8)
1037    }
1038    ///Bits 6:7 - Configurable digital filter for trigger
1039    #[inline(always)]
1040    pub fn trgflt(&self) -> TRGFLT_R {
1041        TRGFLT_R::new(((self.bits >> 6) & 3) as u8)
1042    }
1043    ///Bits 9:11 - Clock prescaler
1044    #[inline(always)]
1045    pub fn presc(&self) -> PRESC_R {
1046        PRESC_R::new(((self.bits >> 9) & 7) as u8)
1047    }
1048    ///Bits 13:15 - Trigger selector
1049    #[inline(always)]
1050    pub fn trigsel(&self) -> TRIGSEL_R {
1051        TRIGSEL_R::new(((self.bits >> 13) & 7) as u8)
1052    }
1053    ///Bits 17:18 - Trigger enable and polarity
1054    #[inline(always)]
1055    pub fn trigen(&self) -> TRIGEN_R {
1056        TRIGEN_R::new(((self.bits >> 17) & 3) as u8)
1057    }
1058    ///Bit 19 - Timeout enable
1059    #[inline(always)]
1060    pub fn timout(&self) -> TIMOUT_R {
1061        TIMOUT_R::new(((self.bits >> 19) & 1) != 0)
1062    }
1063    ///Bit 20 - Waveform shape
1064    #[inline(always)]
1065    pub fn wave(&self) -> WAVE_R {
1066        WAVE_R::new(((self.bits >> 20) & 1) != 0)
1067    }
1068    ///Bit 21 - Waveform shape polarity
1069    #[inline(always)]
1070    pub fn wavpol(&self) -> WAVPOL_R {
1071        WAVPOL_R::new(((self.bits >> 21) & 1) != 0)
1072    }
1073    ///Bit 22 - Registers update mode
1074    #[inline(always)]
1075    pub fn preload(&self) -> PRELOAD_R {
1076        PRELOAD_R::new(((self.bits >> 22) & 1) != 0)
1077    }
1078    ///Bit 23 - counter mode enabled
1079    #[inline(always)]
1080    pub fn countmode(&self) -> COUNTMODE_R {
1081        COUNTMODE_R::new(((self.bits >> 23) & 1) != 0)
1082    }
1083    ///Bit 24 - Encoder mode enable
1084    #[inline(always)]
1085    pub fn enc(&self) -> ENC_R {
1086        ENC_R::new(((self.bits >> 24) & 1) != 0)
1087    }
1088}
1089impl core::fmt::Debug for R {
1090    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1091        f.debug_struct("CFGR")
1092            .field("enc", &self.enc())
1093            .field("countmode", &self.countmode())
1094            .field("preload", &self.preload())
1095            .field("wavpol", &self.wavpol())
1096            .field("wave", &self.wave())
1097            .field("timout", &self.timout())
1098            .field("trigen", &self.trigen())
1099            .field("trigsel", &self.trigsel())
1100            .field("presc", &self.presc())
1101            .field("trgflt", &self.trgflt())
1102            .field("ckflt", &self.ckflt())
1103            .field("ckpol", &self.ckpol())
1104            .field("cksel", &self.cksel())
1105            .finish()
1106    }
1107}
1108impl W {
1109    ///Bit 0 - Clock selector
1110    #[inline(always)]
1111    pub fn cksel(&mut self) -> CKSEL_W<CFGRrs> {
1112        CKSEL_W::new(self, 0)
1113    }
1114    ///Bits 1:2 - Clock Polarity
1115    #[inline(always)]
1116    pub fn ckpol(&mut self) -> CKPOL_W<CFGRrs> {
1117        CKPOL_W::new(self, 1)
1118    }
1119    ///Bits 3:4 - Configurable digital filter for external clock
1120    #[inline(always)]
1121    pub fn ckflt(&mut self) -> CKFLT_W<CFGRrs> {
1122        CKFLT_W::new(self, 3)
1123    }
1124    ///Bits 6:7 - Configurable digital filter for trigger
1125    #[inline(always)]
1126    pub fn trgflt(&mut self) -> TRGFLT_W<CFGRrs> {
1127        TRGFLT_W::new(self, 6)
1128    }
1129    ///Bits 9:11 - Clock prescaler
1130    #[inline(always)]
1131    pub fn presc(&mut self) -> PRESC_W<CFGRrs> {
1132        PRESC_W::new(self, 9)
1133    }
1134    ///Bits 13:15 - Trigger selector
1135    #[inline(always)]
1136    pub fn trigsel(&mut self) -> TRIGSEL_W<CFGRrs> {
1137        TRIGSEL_W::new(self, 13)
1138    }
1139    ///Bits 17:18 - Trigger enable and polarity
1140    #[inline(always)]
1141    pub fn trigen(&mut self) -> TRIGEN_W<CFGRrs> {
1142        TRIGEN_W::new(self, 17)
1143    }
1144    ///Bit 19 - Timeout enable
1145    #[inline(always)]
1146    pub fn timout(&mut self) -> TIMOUT_W<CFGRrs> {
1147        TIMOUT_W::new(self, 19)
1148    }
1149    ///Bit 20 - Waveform shape
1150    #[inline(always)]
1151    pub fn wave(&mut self) -> WAVE_W<CFGRrs> {
1152        WAVE_W::new(self, 20)
1153    }
1154    ///Bit 21 - Waveform shape polarity
1155    #[inline(always)]
1156    pub fn wavpol(&mut self) -> WAVPOL_W<CFGRrs> {
1157        WAVPOL_W::new(self, 21)
1158    }
1159    ///Bit 22 - Registers update mode
1160    #[inline(always)]
1161    pub fn preload(&mut self) -> PRELOAD_W<CFGRrs> {
1162        PRELOAD_W::new(self, 22)
1163    }
1164    ///Bit 23 - counter mode enabled
1165    #[inline(always)]
1166    pub fn countmode(&mut self) -> COUNTMODE_W<CFGRrs> {
1167        COUNTMODE_W::new(self, 23)
1168    }
1169    ///Bit 24 - Encoder mode enable
1170    #[inline(always)]
1171    pub fn enc(&mut self) -> ENC_W<CFGRrs> {
1172        ENC_W::new(self, 24)
1173    }
1174}
1175/**Configuration Register
1176
1177You can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1178
1179See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L562.html#LPTIM1:CFGR)*/
1180pub struct CFGRrs;
1181impl crate::RegisterSpec for CFGRrs {
1182    type Ux = u32;
1183}
1184///`read()` method returns [`cfgr::R`](R) reader structure
1185impl crate::Readable for CFGRrs {}
1186///`write(|w| ..)` method takes [`cfgr::W`](W) writer structure
1187impl crate::Writable for CFGRrs {
1188    type Safety = crate::Unsafe;
1189}
1190///`reset()` method sets CFGR to value 0
1191impl crate::Resettable for CFGRrs {}
stm32l5/stm32l562/lptim1/cfgr.rs

stm32l5/stm32l562/lptim1/
cfgr.rs
