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#[doc = "Reader of register FMC_PCR"] pub type R = crate::R<u32, super::FMC_PCR>; #[doc = "Writer for register FMC_PCR"] pub type W = crate::W<u32, super::FMC_PCR>; #[doc = "Register FMC_PCR `reset()`'s with value 0x18"] impl crate::ResetValue for super::FMC_PCR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x18 } } #[doc = "Reader of field `PWAITEN`"] pub type PWAITEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PWAITEN`"] pub struct PWAITEN_W<'a> { w: &'a mut W, } impl<'a> PWAITEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `PBKEN`"] pub type PBKEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PBKEN`"] pub struct PBKEN_W<'a> { w: &'a mut W, } impl<'a> PBKEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `PTYP`"] pub type PTYP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PTYP`"] pub struct PTYP_W<'a> { w: &'a mut W, } impl<'a> PTYP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `PWID`"] pub type PWID_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PWID`"] pub struct PWID_W<'a> { w: &'a mut W, } impl<'a> PWID_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4); self.w } } #[doc = "Reader of field `ECCEN`"] pub type ECCEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ECCEN`"] pub struct ECCEN_W<'a> { w: &'a mut W, } impl<'a> ECCEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "Reader of field `TCLR`"] pub type TCLR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `TCLR`"] pub struct TCLR_W<'a> { w: &'a mut W, } impl<'a> TCLR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 9)) | (((value as u32) & 0x0f) << 9); self.w } } #[doc = "Reader of field `TAR`"] pub type TAR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `TAR`"] pub struct TAR_W<'a> { w: &'a mut W, } impl<'a> TAR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 13)) | (((value as u32) & 0x0f) << 13); self.w } } #[doc = "Reader of field `ECCPS`"] pub type ECCPS_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ECCPS`"] pub struct ECCPS_W<'a> { w: &'a mut W, } impl<'a> ECCPS_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 17)) | (((value as u32) & 0x07) << 17); self.w } } impl R { #[doc = "Bit 1 - Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:"] #[inline(always)] pub fn pwaiten(&self) -> PWAITEN_R { PWAITEN_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 2 - NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus"] #[inline(always)] pub fn pbken(&self) -> PBKEN_R { PBKEN_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - Memory type"] #[inline(always)] pub fn ptyp(&self) -> PTYP_R { PTYP_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bits 4:5 - Data bus width. These bits define the external memory device width."] #[inline(always)] pub fn pwid(&self) -> PWID_R { PWID_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bit 6 - ECC computation logic enable bit"] #[inline(always)] pub fn eccen(&self) -> ECCEN_R { ECCEN_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bits 9:12 - CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space."] #[inline(always)] pub fn tclr(&self) -> TCLR_R { TCLR_R::new(((self.bits >> 9) & 0x0f) as u8) } #[doc = "Bits 13:16 - ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space."] #[inline(always)] pub fn tar(&self) -> TAR_R { TAR_R::new(((self.bits >> 13) & 0x0f) as u8) } #[doc = "Bits 17:19 - ECC page size. These bits define the page size for the extended ECC:"] #[inline(always)] pub fn eccps(&self) -> ECCPS_R { ECCPS_R::new(((self.bits >> 17) & 0x07) as u8) } } impl W { #[doc = "Bit 1 - Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:"] #[inline(always)] pub fn pwaiten(&mut self) -> PWAITEN_W { PWAITEN_W { w: self } } #[doc = "Bit 2 - NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus"] #[inline(always)] pub fn pbken(&mut self) -> PBKEN_W { PBKEN_W { w: self } } #[doc = "Bit 3 - Memory type"] #[inline(always)] pub fn ptyp(&mut self) -> PTYP_W { PTYP_W { w: self } } #[doc = "Bits 4:5 - Data bus width. These bits define the external memory device width."] #[inline(always)] pub fn pwid(&mut self) -> PWID_W { PWID_W { w: self } } #[doc = "Bit 6 - ECC computation logic enable bit"] #[inline(always)] pub fn eccen(&mut self) -> ECCEN_W { ECCEN_W { w: self } } #[doc = "Bits 9:12 - CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space."] #[inline(always)] pub fn tclr(&mut self) -> TCLR_W { TCLR_W { w: self } } #[doc = "Bits 13:16 - ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space."] #[inline(always)] pub fn tar(&mut self) -> TAR_W { TAR_W { w: self } } #[doc = "Bits 17:19 - ECC page size. These bits define the page size for the extended ECC:"] #[inline(always)] pub fn eccps(&mut self) -> ECCPS_W { ECCPS_W { w: self } } }