stm32l4xx_hal/rcc/
enable.rs

1use super::*;
2
3macro_rules! bus_enable {
4    ($PER:ident => $en:ident) => {
5        impl Enable for crate::pac::$PER {
6            #[inline(always)]
7            fn enable(bus: &mut Self::Bus) {
8                bus.enr().modify(|_, w| w.$en().set_bit());
9                // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
10                cortex_m::asm::dsb(); // TODO: check if needed
11            }
12            #[inline(always)]
13            fn disable(bus: &mut Self::Bus) {
14                bus.enr().modify(|_, w| w.$en().clear_bit());
15            }
16            #[inline(always)]
17            fn is_enabled() -> bool {
18                Self::Bus::new().enr().read().$en().bit_is_set()
19            }
20            #[inline(always)]
21            fn is_disabled() -> bool {
22                Self::Bus::new().enr().read().$en().bit_is_clear()
23            }
24            #[inline(always)]
25            unsafe fn enable_unchecked() {
26                Self::enable(&mut Self::Bus::new());
27            }
28            #[inline(always)]
29            unsafe fn disable_unchecked() {
30                Self::disable(&mut Self::Bus::new());
31            }
32        }
33    };
34}
35
36macro_rules! bus_smenable {
37    ($PER:ident => $smen:ident) => {
38        impl SMEnable for crate::pac::$PER {
39            #[inline(always)]
40            fn enable_in_sleep_mode(bus: &mut Self::Bus) {
41                bus.smenr().modify(|_, w| w.$smen().set_bit());
42                // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
43                cortex_m::asm::dsb();
44            }
45            #[inline(always)]
46            fn disable_in_sleep_mode(bus: &mut Self::Bus) {
47                bus.smenr().modify(|_, w| w.$smen().clear_bit());
48            }
49            #[inline(always)]
50            fn is_enabled_in_sleep_mode() -> bool {
51                Self::Bus::new().smenr().read().$smen().bit_is_set()
52            }
53            #[inline(always)]
54            fn is_disabled_in_sleep_mode() -> bool {
55                Self::Bus::new().smenr().read().$smen().bit_is_clear()
56            }
57            #[inline(always)]
58            unsafe fn enable_in_sleep_mode_unchecked() {
59                Self::enable(&mut Self::Bus::new());
60            }
61            #[inline(always)]
62            unsafe fn disable_in_sleep_mode_unchecked() {
63                Self::disable(&mut Self::Bus::new());
64            }
65        }
66    };
67}
68macro_rules! bus_reset {
69    ($PER:ident => $rst:ident) => {
70        impl Reset for crate::pac::$PER {
71            #[inline(always)]
72            fn reset(bus: &mut Self::Bus) {
73                bus.rstr().modify(|_, w| w.$rst().set_bit());
74                bus.rstr().modify(|_, w| w.$rst().clear_bit());
75            }
76            #[inline(always)]
77            unsafe fn reset_unchecked() {
78                Self::reset(&mut Self::Bus::new());
79            }
80        }
81    };
82}
83
84macro_rules! bus {
85    ($($PER:ident => ($busX:ty, $($en:ident)?, $($smen:ident)?, $($rst:ident)?),)+) => {
86        $(
87            impl crate::Sealed for crate::pac::$PER {}
88            impl RccBus for crate::pac::$PER {
89                type Bus = $busX;
90            }
91            $(bus_enable!($PER => $en);)?
92            $(bus_smenable!($PER => $smen);)?
93            $(bus_reset!($PER => $rst);)?
94        )+
95    };
96}
97
98bus! {
99    DMA1 => (AHB1, dma1en, dma1smen, dma1rst), // 0
100    DMA2 => (AHB1, dma2en, dma2smen, dma2rst), // 1
101    FLASH => (AHB1, flashen, flashsmen, flashrst), // 8
102    CRC => (AHB1, crcen, crcsmen, crcrst), // 12
103    TSC => (AHB1, tscen, tscsmen, tscrst), // 16
104
105    GPIOA => (AHB2, gpioaen, gpioasmen, gpioarst), // 0
106    GPIOB => (AHB2, gpioben, gpiobsmen, gpiobrst), // 1
107    GPIOC => (AHB2, gpiocen, gpiocsmen, gpiocrst), // 2
108    GPIOD => (AHB2, gpioden, gpiodsmen, gpiodrst), // 3
109    GPIOE => (AHB2, gpioeen, gpioesmen, gpioerst), // 4
110    GPIOH => (AHB2, gpiohen, gpiohsmen, gpiohrst), // 7
111    AES => (AHB2, aesen, aessmen, aesrst), // 16
112    RNG => (AHB2, rngen, rngsmen, rngrst), // 18
113
114    TIM2 => (APB1R1, tim2en, tim2smen, tim2rst), // 0
115    TIM6 => (APB1R1, tim6en, tim6smen, tim6rst), // 4
116    TIM7 => (APB1R1, tim7en, tim7smen, tim7rst), // 5
117    WWDG => (APB1R1, wwdgen, wwdgsmen,), // 11
118    SPI2 => (APB1R1, spi2en, spi2smen, spi2rst), // 14
119    SPI3 => (APB1R1, spi3en, sp3smen, spi3rst), // 15 // TODO: fix typo
120    USART2 => (APB1R1, usart2en, usart2smen, usart2rst), // 17
121    USART3 => (APB1R1, usart3en, usart3smen, usart3rst), // 18
122    I2C1 => (APB1R1, i2c1en, i2c1smen, i2c1rst), // 21
123    I2C2 => (APB1R1, i2c2en, i2c2smen, i2c2rst), // 22
124    I2C3 => (APB1R1, i2c3en, i2c3smen, i2c3rst), // 23
125    CAN1 => (APB1R1, can1en, can1smen, can1rst), // 25
126    PWR => (APB1R1, pwren, pwrsmen, pwrrst), // 28
127    OPAMP => (APB1R1, opampen, opampsmen, opamprst), // 30
128    LPTIM1 => (APB1R1, lptim1en, lptim1smen, lptim1rst), // 31
129
130    LPUART1 => (APB1R2, lpuart1en, lpuart1smen, lpuart1rst), // 0
131    LPTIM2 => (APB1R2, lptim2en, lptim2smen, lptim2rst), // 5
132
133    SYSCFG => (APB2, syscfgen, syscfgsmen, syscfgrst), // 0
134    TIM1 => (APB2, tim1en, tim1smen, tim1rst), // 11
135    SPI1 => (APB2, spi1en, spi1smen, spi1rst), // 12
136    USART1 => (APB2, usart1en, usart1smen, usart1rst), // 14
137    TIM15 => (APB2, tim15en, tim15smen, tim15rst), // 16
138    TIM16 => (APB2, tim16en, tim16smen, tim16rst), // 17
139    SAI1 => (APB2, sai1en, sai1smen, sai1rst), // 21
140}
141
142// L4x1, L4x2, L4x3, L4x5 or L4x6
143#[cfg(not(any(
144    // feature = "stm32l4p5",
145    // feature = "stm32l4q5",
146    // feature = "stm32l4r5",
147    // feature = "stm32l4s5",
148    // feature = "stm32l4r7",
149    // feature = "stm32l4s7",
150    feature = "stm32l4r9",
151    feature = "stm32l4s9",
152)))]
153bus! {
154    ADC1 => (AHB2, adcen, adcfssmen, adcrst), // 13
155
156    LCD => (APB1R1, lcden, lcdsmen, lcdrst), // 9
157
158    SWPMI1 => (APB1R2, swpmi1en, swpmi1smen, swpmi1rst), // 2
159
160    FIREWALL => (APB2, firewallen,,), // 7
161}
162
163// L4+
164#[cfg(any(
165    // feature = "stm32l4p5",
166    // feature = "stm32l4q5",
167    // feature = "stm32l4r5",
168    // feature = "stm32l4s5",
169    // feature = "stm32l4r7",
170    // feature = "stm32l4s7",
171    feature = "stm32l4r9",
172    feature = "stm32l4s9",
173))]
174bus! {
175    ADC => (AHB2, adcen, adcfssmen, adcrst), // 13
176
177    FIREWALL => (APB2, fwen,,), // 7
178    LTCD => (APB2, ltdcen, ltdcsmen, ltdcrst), // 26
179}
180
181// L4x5 or L4x6
182#[cfg(any(
183    feature = "stm32l475",
184    feature = "stm32l476",
185    feature = "stm32l485",
186    feature = "stm32l486",
187    feature = "stm32l496",
188    feature = "stm32l4a6",
189    // feature = "stm32l4p5",
190    // feature = "stm32l4q5",
191    // feature = "stm32l4r5",
192    // feature = "stm32l4s5",
193    // feature = "stm32l4r7",
194    // feature = "stm32l4s7",
195    feature = "stm32l4r9",
196    feature = "stm32l4s9",
197))]
198bus! {
199    GPIOF => (AHB2, gpiofen, gpiofsmen, gpiofrst), // 5
200    GPIOG => (AHB2, gpiogen, gpiogsmen, gpiogrst), // 6
201
202    FMC => (AHB3, fmcen, fmcsmen, fmcrst), // 0
203
204    TIM3 => (APB1R1, tim3en, tim3smen, tim3rst), // 1
205    TIM4 => (APB1R1, tim4en, tim4smen, tim4rst), // 2
206    TIM5 => (APB1R1, tim5en, tim5smen, tim5rst), // 3
207    UART4 => (APB1R1, uart4en, uart4smen, uart4rst), // 19
208    UART5 => (APB1R1, uart5en, uart5smen, uart5rst), // 20
209
210    TIM8 => (APB2, tim8en, tim8smen, tim8rst), // 13
211    TIM17 => (APB2, tim17en, tim17smen, tim17rst), // 18
212    SAI2 => (APB2, sai2en, sai2smen, sai2rst), // 22
213}
214
215// L4x1 or L4x2
216#[cfg(any(
217    feature = "stm32l431",
218    feature = "stm32l451",
219    feature = "stm32l471",
220    feature = "stm32l412",
221    feature = "stm32l422",
222    feature = "stm32l432",
223    feature = "stm32l442",
224    feature = "stm32l452",
225    feature = "stm32l462",
226))]
227bus! {
228    UART4 => (APB1R1, uart4en, uart4smen, usart4rst), // 19 // TODO: fix typo
229
230    I2C4 => (APB1R2, i2c4en,, i2c4rst), // 1 // TODO: fix absent
231}
232
233// L4x1, L4x2, L4x3, or L4x5
234#[cfg(any(
235    feature = "stm32l431",
236    feature = "stm32l451",
237    feature = "stm32l471",
238    feature = "stm32l412",
239    feature = "stm32l422",
240    feature = "stm32l432",
241    feature = "stm32l442",
242    feature = "stm32l452",
243    feature = "stm32l462",
244    feature = "stm32l433",
245    feature = "stm32l443",
246    feature = "stm32l475",
247))]
248bus! {
249    DAC1 => (APB1R1, dac1en, dac1smen, dac1rst), // 29
250
251    SDMMC => (APB2, sdmmcen, sdmmcsmen, sdmmcrst), // 10
252}
253
254// L4x1, L4x2, L4x5, or L4x6
255#[cfg(not(any(
256    feature = "stm32l433",
257    feature = "stm32l443",
258    // feature = "stm32l4p5",
259    // feature = "stm32l4q5",
260    // feature = "stm32l4r5",
261    // feature = "stm32l4s5",
262    // feature = "stm32l4r7",
263    // feature = "stm32l4s7",
264    feature = "stm32l4r9",
265    feature = "stm32l4s9",
266    )))]
267bus! {
268    ADC2 => (AHB2, adcen, adcfssmen, adcrst), // 13
269    QUADSPI => (AHB3, qspien, qspismen, qspirst), // 8
270}
271
272// L4x1, L4x2, L4x3, or L4x6 (L4+ assumed)
273#[cfg(not(any(feature = "stm32l475",)))]
274bus! {
275    CRS => (APB1R1, crsen,,), // 24 // TODO: fix absent
276}
277
278// L4x1, or L4x3
279#[cfg(any(
280    feature = "stm32l412",
281    feature = "stm32l422",
282    feature = "stm32l432",
283    feature = "stm32l442",
284    feature = "stm32l452",
285    feature = "stm32l462",
286    feature = "stm32l433",
287    feature = "stm32l443",
288))]
289bus! {
290    USB => (APB1R1, usbfsen, usbfssmen, usbfsrst), // 26
291}
292
293// L4x1
294#[cfg(any(feature = "stm32l431", feature = "stm32l451", feature = "stm32l471",))]
295bus! {
296    TIM3 => (APB1R1, tim3en,,), // 1 // TODO: absent smen, rst
297    USB_FS => (APB1R1, usbf, usbfssmen, usbfsrst), // 26 // TODO: fix typo
298}
299
300// L4x2
301#[cfg(any(
302    feature = "stm32l412",
303    feature = "stm32l422",
304    feature = "stm32l432",
305    feature = "stm32l442",
306    feature = "stm32l452",
307    feature = "stm32l462",
308))]
309bus! {
310    TIM3 => (APB1R1, tim3en,, tim3rst), // 1 // TODO: fix absent
311}
312
313// L4x5
314#[cfg(any(feature = "stm32l475"))]
315bus! {
316    DFSDM => (APB2, dfsdmen, dfsdmsmen, dfsdmrst), // 24
317}
318
319// L4x6 (L4+ assumed)
320#[cfg(any(
321    feature = "stm32l476",
322    feature = "stm32l486",
323    feature = "stm32l496",
324    feature = "stm32l4a6",
325    // feature = "stm32l4p5",
326    // feature = "stm32l4q5",
327    // feature = "stm32l4r5",
328    // feature = "stm32l4s5",
329    // feature = "stm32l4r7",
330    // feature = "stm32l4s7",
331    feature = "stm32l4r9",
332    feature = "stm32l4s9",
333))]
334bus! {
335    DMA2D => (AHB1, dma2den, dma2dsmen, dma2drst), // 17
336
337    GPIOI => (AHB2, gpioien, gpioismen, gpioirst), // 8
338    OTG_FS_GLOBAL => (AHB2, otgfsen, otgfssmen, otgfsrst), // 12 // TODO: absent in x5
339    DCMI => (AHB2, dcmien, dcmismen, dcmirst), // 14
340
341    DAC => (APB1R1, dac1en, dac1smen, dac1rst), // 29
342
343    I2C4 => (APB1R2, i2c4en, i2c4smen, i2c4rst), // 1
344}
345
346#[cfg(any(
347    feature = "stm32l476",
348    feature = "stm32l486",
349    feature = "stm32l496",
350    feature = "stm32l4a6",
351))]
352bus! {
353    CAN2 => (APB1R1, can2en, can2smen, can2rst), // 26
354
355    HASH => (AHB2, hash1en, hash1smen, hash1rst), // 17
356
357    SDMMC1 => (APB2, sdmmcen, sdmmcsmen, sdmmcrst), // 10
358    DFSDM1 => (APB2, dfsdmen, dfsdmsmen, dfsdmrst), // 24
359}
360
361#[cfg(any(
362    // feature = "stm32l4p5",
363    // feature = "stm32l4q5",
364    // feature = "stm32l4r5",
365    // feature = "stm32l4s5",
366    // feature = "stm32l4r7",
367    // feature = "stm32l4s7",
368    feature = "stm32l4r9",
369    feature = "stm32l4s9",
370))]
371bus! {
372    HASH => (AHB2, hashen, hashsmen, hashrst), // 17
373    SDMMC1 => (AHB2, sdmmc1en, sdmmc1smen, sdmmc1rst), // 22
374
375    DFSDM1 => (APB2, dfsdm1en, dfsdm1smen, dfsdm1rst), // 24
376}
stm32l4xx_hal/rcc/enable.rs

stm32l4xx_hal/rcc/
enable.rs
