stm32l4xx_hal/rtc/
rtc2.rs

1use crate::pac::RTC;
2
3pub fn reset_gpio(rtc: &RTC) {
4    rtc.or
5        .modify(|_, w| w.rtc_alarm_type().clear_bit().rtc_out_rmp().clear_bit());
6}
7
8/// true if initf bit indicates RTC peripheral is in init mode
9pub fn is_init_mode(rtc: &RTC) -> bool {
10    rtc.isr.read().initf().bit_is_set()
11}
12
13/// to update calendar date/time, time format, and prescaler configuration, RTC must be in init mode
14pub fn enter_init_mode(rtc: &RTC) {
15    rtc.isr.modify(|_, w| w.init().set_bit());
16}
17
18/// counting will restart in 4 RTCCLK cycles
19pub fn exit_init_mode(rtc: &RTC) {
20    rtc.isr.modify(|_, w| w.init().clear_bit()); // Exits init mode
21}
22
23/// has wakeup timer expired?
24pub fn is_wakeup_timer_flag_set(rtc: &RTC) -> bool {
25    rtc.isr.read().wutf().bit_is_set()
26}
27
28pub fn is_wakeup_timer_write_flag_set(rtc: &RTC) -> bool {
29    rtc.isr.read().wutwf().bit_is_set()
30}
31
32/// clear the wakeup timer flag
33pub fn clear_wakeup_timer_flag(rtc: &RTC) {
34    rtc.isr.modify(|_, w| w.wutf().clear_bit());
35}
36
37/// has alarm A been triggered
38pub fn is_alarm_a_flag_set(rtc: &RTC) -> bool {
39    rtc.isr.read().alraf().bit_is_set()
40}
41
42/// clear the alarm A flag
43pub fn clear_alarm_a_flag(rtc: &RTC) {
44    rtc.isr.modify(|_, w| w.alraf().clear_bit());
45}
46
47/// has alarm B been triggered?
48pub fn is_alarm_b_flag_set(rtc: &RTC) -> bool {
49    rtc.isr.read().alrbf().bit_is_set()
50}
51
52/// clear the alarm B flag
53pub fn clear_alarm_b_flag(rtc: &RTC) {
54    rtc.isr.modify(|_, w| w.alrbf().clear_bit());
55}
56
57/// has timestamp event triggered
58pub fn is_timestamp_flag_set(rtc: &RTC) -> bool {
59    rtc.isr.read().tsf().bit_is_set()
60}
61
62/// clear the timestamp event flag
63pub fn clear_timestamp_flag(rtc: &RTC) {
64    rtc.isr.modify(|_, w| w.tsf().clear_bit());
65}
66
67pub fn is_alarm_a_accessible(rtc: &RTC) -> bool {
68    rtc.isr.read().alrawf().bit_is_set()
69}
70
71pub fn is_alarm_b_accessible(rtc: &RTC) -> bool {
72    rtc.isr.read().alrbwf().bit_is_set()
73}
74
75// AN7459
76// L4 series except L41/2 has 20 backup registers
77// L41/2, L4P/Q and L4R/S have 32 backup registers
78#[cfg(not(any(
79    feature = "stm32l4r5",
80    feature = "stm32l4s5",
81    feature = "stm32l4r7",
82    feature = "stm32l4s7",
83    feature = "stm32l4r9",
84    feature = "stm32l4s9"
85)))]
86pub const BACKUP_REGISTER_COUNT: usize = 20;
87#[cfg(any(
88    feature = "stm32l4r5",
89    feature = "stm32l4s5",
90    feature = "stm32l4r7",
91    feature = "stm32l4s7",
92    feature = "stm32l4r9",
93    feature = "stm32l4s9"
94))]
95pub const BACKUP_REGISTER_COUNT: usize = 32;
96
97/// Read content of the backup register.
98///
99/// The registers retain their values during wakes from standby mode or system resets. They also
100/// retain their value when Vdd is switched off as long as V_BAT is powered.
101pub fn read_backup_register(rtc: &RTC, register: usize) -> Option<u32> {
102    if register < BACKUP_REGISTER_COUNT {
103        Some(rtc.bkpr[register].read().bits())
104    } else {
105        None
106    }
107}
108
109/// Set content of the backup register.
110///
111/// The registers retain their values during wakes from standby mode or system resets. They also
112/// retain their value when Vdd is switched off as long as V_BAT is powered.
113pub fn write_backup_register(rtc: &RTC, register: usize, value: u32) {
114    if register < BACKUP_REGISTER_COUNT {
115        unsafe { rtc.bkpr[register].write(|w| w.bits(value)) }
116    }
117}
stm32l4xx_hal/rtc/rtc2.rs

stm32l4xx_hal/rtc/
rtc2.rs
