Expand description
Serial Peripheral Interface (SPI) bus
The PACs and SVDs are not set up granularity enough to handle all peripheral configurations. SPI2 is enabled for stm32l4x2 feature at a HAL level even though some variants do and some don’t have it (L432xx and L442xx don’t, L452xx does). Users of this MCU variant that don’t have it shouldn’t attempt to use it. Relevant info is on user-manual level.
Structs§
- Spi
- SPI peripheral operating in full duplex master mode
- SpiPayload
Enums§
- Error
- SPI error
Traits§
- MisoPin
- MISO pin. This trait is sealed and cannot be implemented.
- MosiPin
- MOSI pin. This trait is sealed and cannot be implemented.
- SckPin
- SCK pin. This trait is sealed and cannot be implemented.