stm32l4xx_hal/
pwr.rs

1//! Power management
2
3use crate::rcc::{Enable, APB1R1};
4use crate::stm32::{pwr, PWR};
5
6pub struct Pwr {
7    pub cr1: CR1,
8    pub cr2: CR2,
9    pub cr3: CR3,
10    pub cr4: CR4,
11}
12
13/// Extension trait that constrains the `PWR` peripheral
14pub trait PwrExt {
15    /// Constrains the `PWR` peripheral so it plays nicely with the other abstractions
16    fn constrain(self, _: &mut APB1R1) -> Pwr;
17}
18
19impl PwrExt for PWR {
20    fn constrain(self, apb1r1: &mut APB1R1) -> Pwr {
21        // Enable the peripheral clock
22        PWR::enable(apb1r1);
23        Pwr {
24            cr1: CR1 { _0: () },
25            cr2: CR2 { _0: () },
26            cr3: CR3 { _0: () },
27            cr4: CR4 { _0: () },
28        }
29    }
30}
31
32/// CR1
33pub struct CR1 {
34    _0: (),
35}
36
37impl CR1 {
38    // TODO remove `allow`
39    #[allow(dead_code)]
40    pub(crate) fn reg(&mut self) -> &pwr::CR1 {
41        // NOTE(unsafe) this proxy grants exclusive access to this register
42        unsafe { &(*PWR::ptr()).cr1 }
43    }
44}
45/// CR2
46pub struct CR2 {
47    _0: (),
48}
49
50impl CR2 {
51    // TODO remove `allow`
52    #[allow(dead_code)]
53    pub(crate) fn reg(&mut self) -> &pwr::CR2 {
54        // NOTE(unsafe) this proxy grants exclusive access to this register
55        unsafe { &(*PWR::ptr()).cr2 }
56    }
57}
58/// CR3
59pub struct CR3 {
60    _0: (),
61}
62
63impl CR3 {
64    // TODO remove `allow`
65    #[allow(dead_code)]
66    pub(crate) fn reg(&mut self) -> &pwr::CR3 {
67        // NOTE(unsafe) this proxy grants exclusive access to this register
68        unsafe { &(*PWR::ptr()).cr3 }
69    }
70}
71/// CR4
72pub struct CR4 {
73    _0: (),
74}
75
76impl CR4 {
77    // TODO remove `allow`
78    #[allow(dead_code)]
79    pub(crate) fn reg(&mut self) -> &pwr::CR4 {
80        // NOTE(unsafe) this proxy grants exclusive access to this register
81        unsafe { &(*PWR::ptr()).cr4 }
82    }
83}
stm32l4xx_hal/pwr.rs

stm32l4xx_hal/
pwr.rs
