Struct stm32l4xx_hal::stm32::rcc::pllcfgr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn pllr(&self) -> PLLRR

Bits 25:26 - Main PLL division factor for PLLCLK (system clock)

pub fn pllren(&self) -> PLLRENR

Bit 24 - Main PLL PLLCLK output enable

pub fn pllq(&self) -> PLLQR

Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)

pub fn pllqen(&self) -> PLLQENR

Bit 20 - Main PLL PLLUSB1CLK output enable

pub fn pllp(&self) -> PLLPR

Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

pub fn pllpen(&self) -> PLLPENR

Bit 16 - Main PLL PLLSAI3CLK output enable

pub fn plln(&self) -> PLLNR

Bits 8:14 - Main PLL multiplication factor for VCO

pub fn pllm(&self) -> PLLMR

Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&self) -> PLLSRCR

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source

pub fn pllpdiv(&self) -> PLLPDIVR

Bits 27:31 - Main PLL division factor for PLLSAI2CLK