Struct stm32l4xx_hal::stm32::dfsdm::dfsdm0_cr1::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn awfsel(&self) -> AWFSELR

Bit 30 - Analog watchdog fast mode select

pub fn fast(&self) -> FASTR

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&self) -> RCHR

Bits 24:26 - Regular channel selection

pub fn rdmaen(&self) -> RDMAENR

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&self) -> RSYNCR

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&self) -> RCONTR

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&self) -> RSWSTARTR

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&self) -> JEXTENR

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&self) -> JEXTSELR

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&self) -> JDMAENR

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&self) -> JSCANR

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&self) -> JSYNCR

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&self) -> JSWSTARTR

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&self) -> DFENR

Bit 0 - DFSDM enable