Struct stm32l4x6::dfsdm::dfsdm1_cr1::W

pub struct W { /* private fields */ }

Value to write to the register

Implementations

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn awfsel(&mut self) -> _AWFSELW<'_>

Bit 30 - Analog watchdog fast mode select

pub fn fast(&mut self) -> _FASTW<'_>

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&mut self) -> _RCHW<'_>

Bits 24:26 - Regular channel selection

pub fn rdmaen(&mut self) -> _RDMAENW<'_>

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&mut self) -> _RSYNCW<'_>

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&mut self) -> _RCONTW<'_>

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&mut self) -> _RSWSTARTW<'_>

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&mut self) -> _JEXTENW<'_>

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> _JEXTSELW<'_>

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&mut self) -> _JDMAENW<'_>

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&mut self) -> _JSCANW<'_>

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&mut self) -> _JSYNCW<'_>

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&mut self) -> _JSWSTARTW<'_>

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&mut self) -> _DFENW<'_>

Bit 0 - DFSDM enable