stm32l4x2_pac/wwdg/
cfr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CFR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = "Possible values of the field `EWI`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum EWIR {
48    #[doc = "interrupt occurs whenever the counter reaches the value 0x40"]
49    ENABLE,
50    #[doc = r" Reserved"]
51    _Reserved(bool),
52}
53impl EWIR {
54    #[doc = r" Returns `true` if the bit is clear (0)"]
55    #[inline]
56    pub fn bit_is_clear(&self) -> bool {
57        !self.bit()
58    }
59    #[doc = r" Returns `true` if the bit is set (1)"]
60    #[inline]
61    pub fn bit_is_set(&self) -> bool {
62        self.bit()
63    }
64    #[doc = r" Value of the field as raw bits"]
65    #[inline]
66    pub fn bit(&self) -> bool {
67        match *self {
68            EWIR::ENABLE => true,
69            EWIR::_Reserved(bits) => bits,
70        }
71    }
72    #[allow(missing_docs)]
73    #[doc(hidden)]
74    #[inline]
75    pub fn _from(value: bool) -> EWIR {
76        match value {
77            true => EWIR::ENABLE,
78            i => EWIR::_Reserved(i),
79        }
80    }
81    #[doc = "Checks if the value of the field is `ENABLE`"]
82    #[inline]
83    pub fn is_enable(&self) -> bool {
84        *self == EWIR::ENABLE
85    }
86}
87#[doc = r" Value of the field"]
88pub struct WR {
89    bits: u8,
90}
91impl WR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bits(&self) -> u8 {
95        self.bits
96    }
97}
98#[doc = "Possible values of the field `WDGTB`"]
99#[derive(Clone, Copy, Debug, PartialEq)]
100pub enum WDGTBR {
101    #[doc = "Counter clock (PCLK1 div 4096) div 1"]
102    DIV1,
103    #[doc = "Counter clock (PCLK1 div 4096) div 2"]
104    DIV2,
105    #[doc = "Counter clock (PCLK1 div 4096) div 4"]
106    DIV4,
107    #[doc = "Counter clock (PCLK1 div 4096) div 8"]
108    DIV8,
109}
110impl WDGTBR {
111    #[doc = r" Value of the field as raw bits"]
112    #[inline]
113    pub fn bits(&self) -> u8 {
114        match *self {
115            WDGTBR::DIV1 => 0,
116            WDGTBR::DIV2 => 1,
117            WDGTBR::DIV4 => 2,
118            WDGTBR::DIV8 => 3,
119        }
120    }
121    #[allow(missing_docs)]
122    #[doc(hidden)]
123    #[inline]
124    pub fn _from(value: u8) -> WDGTBR {
125        match value {
126            0 => WDGTBR::DIV1,
127            1 => WDGTBR::DIV2,
128            2 => WDGTBR::DIV4,
129            3 => WDGTBR::DIV8,
130            _ => unreachable!(),
131        }
132    }
133    #[doc = "Checks if the value of the field is `DIV1`"]
134    #[inline]
135    pub fn is_div1(&self) -> bool {
136        *self == WDGTBR::DIV1
137    }
138    #[doc = "Checks if the value of the field is `DIV2`"]
139    #[inline]
140    pub fn is_div2(&self) -> bool {
141        *self == WDGTBR::DIV2
142    }
143    #[doc = "Checks if the value of the field is `DIV4`"]
144    #[inline]
145    pub fn is_div4(&self) -> bool {
146        *self == WDGTBR::DIV4
147    }
148    #[doc = "Checks if the value of the field is `DIV8`"]
149    #[inline]
150    pub fn is_div8(&self) -> bool {
151        *self == WDGTBR::DIV8
152    }
153}
154#[doc = "Values that can be written to the field `EWI`"]
155pub enum EWIW {
156    #[doc = "interrupt occurs whenever the counter reaches the value 0x40"]
157    ENABLE,
158}
159impl EWIW {
160    #[allow(missing_docs)]
161    #[doc(hidden)]
162    #[inline]
163    pub fn _bits(&self) -> bool {
164        match *self {
165            EWIW::ENABLE => true,
166        }
167    }
168}
169#[doc = r" Proxy"]
170pub struct _EWIW<'a> {
171    w: &'a mut W,
172}
173impl<'a> _EWIW<'a> {
174    #[doc = r" Writes `variant` to the field"]
175    #[inline]
176    pub fn variant(self, variant: EWIW) -> &'a mut W {
177        {
178            self.bit(variant._bits())
179        }
180    }
181    #[doc = "interrupt occurs whenever the counter reaches the value 0x40"]
182    #[inline]
183    pub fn enable(self) -> &'a mut W {
184        self.variant(EWIW::ENABLE)
185    }
186    #[doc = r" Sets the field bit"]
187    pub fn set_bit(self) -> &'a mut W {
188        self.bit(true)
189    }
190    #[doc = r" Clears the field bit"]
191    pub fn clear_bit(self) -> &'a mut W {
192        self.bit(false)
193    }
194    #[doc = r" Writes raw bits to the field"]
195    #[inline]
196    pub fn bit(self, value: bool) -> &'a mut W {
197        const MASK: bool = true;
198        const OFFSET: u8 = 9;
199        self.w.bits &= !((MASK as u32) << OFFSET);
200        self.w.bits |= ((value & MASK) as u32) << OFFSET;
201        self.w
202    }
203}
204#[doc = r" Proxy"]
205pub struct _WW<'a> {
206    w: &'a mut W,
207}
208impl<'a> _WW<'a> {
209    #[doc = r" Writes raw bits to the field"]
210    #[inline]
211    pub fn bits(self, value: u8) -> &'a mut W {
212        const MASK: u8 = 127;
213        const OFFSET: u8 = 0;
214        self.w.bits &= !((MASK as u32) << OFFSET);
215        self.w.bits |= ((value & MASK) as u32) << OFFSET;
216        self.w
217    }
218}
219#[doc = "Values that can be written to the field `WDGTB`"]
220pub enum WDGTBW {
221    #[doc = "Counter clock (PCLK1 div 4096) div 1"]
222    DIV1,
223    #[doc = "Counter clock (PCLK1 div 4096) div 2"]
224    DIV2,
225    #[doc = "Counter clock (PCLK1 div 4096) div 4"]
226    DIV4,
227    #[doc = "Counter clock (PCLK1 div 4096) div 8"]
228    DIV8,
229}
230impl WDGTBW {
231    #[allow(missing_docs)]
232    #[doc(hidden)]
233    #[inline]
234    pub fn _bits(&self) -> u8 {
235        match *self {
236            WDGTBW::DIV1 => 0,
237            WDGTBW::DIV2 => 1,
238            WDGTBW::DIV4 => 2,
239            WDGTBW::DIV8 => 3,
240        }
241    }
242}
243#[doc = r" Proxy"]
244pub struct _WDGTBW<'a> {
245    w: &'a mut W,
246}
247impl<'a> _WDGTBW<'a> {
248    #[doc = r" Writes `variant` to the field"]
249    #[inline]
250    pub fn variant(self, variant: WDGTBW) -> &'a mut W {
251        {
252            self.bits(variant._bits())
253        }
254    }
255    #[doc = "Counter clock (PCLK1 div 4096) div 1"]
256    #[inline]
257    pub fn div1(self) -> &'a mut W {
258        self.variant(WDGTBW::DIV1)
259    }
260    #[doc = "Counter clock (PCLK1 div 4096) div 2"]
261    #[inline]
262    pub fn div2(self) -> &'a mut W {
263        self.variant(WDGTBW::DIV2)
264    }
265    #[doc = "Counter clock (PCLK1 div 4096) div 4"]
266    #[inline]
267    pub fn div4(self) -> &'a mut W {
268        self.variant(WDGTBW::DIV4)
269    }
270    #[doc = "Counter clock (PCLK1 div 4096) div 8"]
271    #[inline]
272    pub fn div8(self) -> &'a mut W {
273        self.variant(WDGTBW::DIV8)
274    }
275    #[doc = r" Writes raw bits to the field"]
276    #[inline]
277    pub fn bits(self, value: u8) -> &'a mut W {
278        const MASK: u8 = 3;
279        const OFFSET: u8 = 7;
280        self.w.bits &= !((MASK as u32) << OFFSET);
281        self.w.bits |= ((value & MASK) as u32) << OFFSET;
282        self.w
283    }
284}
285impl R {
286    #[doc = r" Value of the register as raw bits"]
287    #[inline]
288    pub fn bits(&self) -> u32 {
289        self.bits
290    }
291    #[doc = "Bit 9 - Early wakeup interrupt"]
292    #[inline]
293    pub fn ewi(&self) -> EWIR {
294        EWIR::_from({
295            const MASK: bool = true;
296            const OFFSET: u8 = 9;
297            ((self.bits >> OFFSET) & MASK as u32) != 0
298        })
299    }
300    #[doc = "Bits 0:6 - 7-bit window value"]
301    #[inline]
302    pub fn w(&self) -> WR {
303        let bits = {
304            const MASK: u8 = 127;
305            const OFFSET: u8 = 0;
306            ((self.bits >> OFFSET) & MASK as u32) as u8
307        };
308        WR { bits }
309    }
310    #[doc = "Bits 7:8 - Timer base"]
311    #[inline]
312    pub fn wdgtb(&self) -> WDGTBR {
313        WDGTBR::_from({
314            const MASK: u8 = 3;
315            const OFFSET: u8 = 7;
316            ((self.bits >> OFFSET) & MASK as u32) as u8
317        })
318    }
319}
320impl W {
321    #[doc = r" Reset value of the register"]
322    #[inline]
323    pub fn reset_value() -> W {
324        W { bits: 127 }
325    }
326    #[doc = r" Writes raw bits to the register"]
327    #[inline]
328    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
329        self.bits = bits;
330        self
331    }
332    #[doc = "Bit 9 - Early wakeup interrupt"]
333    #[inline]
334    pub fn ewi(&mut self) -> _EWIW {
335        _EWIW { w: self }
336    }
337    #[doc = "Bits 0:6 - 7-bit window value"]
338    #[inline]
339    pub fn w(&mut self) -> _WW {
340        _WW { w: self }
341    }
342    #[doc = "Bits 7:8 - Timer base"]
343    #[inline]
344    pub fn wdgtb(&mut self) -> _WDGTBW {
345        _WDGTBW { w: self }
346    }
347}
stm32l4x2_pac/wwdg/cfr.rs

stm32l4x2_pac/wwdg/
cfr.rs
