1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR3 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `WUFIE`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum WUFIER {
48 #[doc = "Interrupt is inhibited"]
49 DISABLED,
50 #[doc = "An USART interrupt is generated whenever WUF=1 in the ISR register"]
51 ENABLED,
52}
53impl WUFIER {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 WUFIER::DISABLED => false,
69 WUFIER::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> WUFIER {
76 match value {
77 false => WUFIER::DISABLED,
78 true => WUFIER::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == WUFIER::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == WUFIER::ENABLED
90 }
91}
92#[doc = "Possible values of the field `WUS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum WUSR {
95 #[doc = "WUF active on address match"]
96 ADDRESS,
97 #[doc = "WuF active on Start bit detection"]
98 START,
99 #[doc = "WUF active on RXNE"]
100 RXNE,
101 #[doc = r" Reserved"]
102 _Reserved(u8),
103}
104impl WUSR {
105 #[doc = r" Value of the field as raw bits"]
106 #[inline]
107 pub fn bits(&self) -> u8 {
108 match *self {
109 WUSR::ADDRESS => 0,
110 WUSR::START => 2,
111 WUSR::RXNE => 3,
112 WUSR::_Reserved(bits) => bits,
113 }
114 }
115 #[allow(missing_docs)]
116 #[doc(hidden)]
117 #[inline]
118 pub fn _from(value: u8) -> WUSR {
119 match value {
120 0 => WUSR::ADDRESS,
121 2 => WUSR::START,
122 3 => WUSR::RXNE,
123 i => WUSR::_Reserved(i),
124 }
125 }
126 #[doc = "Checks if the value of the field is `ADDRESS`"]
127 #[inline]
128 pub fn is_address(&self) -> bool {
129 *self == WUSR::ADDRESS
130 }
131 #[doc = "Checks if the value of the field is `START`"]
132 #[inline]
133 pub fn is_start(&self) -> bool {
134 *self == WUSR::START
135 }
136 #[doc = "Checks if the value of the field is `RXNE`"]
137 #[inline]
138 pub fn is_rxne(&self) -> bool {
139 *self == WUSR::RXNE
140 }
141}
142#[doc = r" Value of the field"]
143pub struct SCARCNTR {
144 bits: u8,
145}
146impl SCARCNTR {
147 #[doc = r" Value of the field as raw bits"]
148 #[inline]
149 pub fn bits(&self) -> u8 {
150 self.bits
151 }
152}
153#[doc = "Possible values of the field `DEP`"]
154#[derive(Clone, Copy, Debug, PartialEq)]
155pub enum DEPR {
156 #[doc = "DE signal is active high"]
157 HIGH,
158 #[doc = "DE signal is active low"]
159 LOW,
160}
161impl DEPR {
162 #[doc = r" Returns `true` if the bit is clear (0)"]
163 #[inline]
164 pub fn bit_is_clear(&self) -> bool {
165 !self.bit()
166 }
167 #[doc = r" Returns `true` if the bit is set (1)"]
168 #[inline]
169 pub fn bit_is_set(&self) -> bool {
170 self.bit()
171 }
172 #[doc = r" Value of the field as raw bits"]
173 #[inline]
174 pub fn bit(&self) -> bool {
175 match *self {
176 DEPR::HIGH => false,
177 DEPR::LOW => true,
178 }
179 }
180 #[allow(missing_docs)]
181 #[doc(hidden)]
182 #[inline]
183 pub fn _from(value: bool) -> DEPR {
184 match value {
185 false => DEPR::HIGH,
186 true => DEPR::LOW,
187 }
188 }
189 #[doc = "Checks if the value of the field is `HIGH`"]
190 #[inline]
191 pub fn is_high(&self) -> bool {
192 *self == DEPR::HIGH
193 }
194 #[doc = "Checks if the value of the field is `LOW`"]
195 #[inline]
196 pub fn is_low(&self) -> bool {
197 *self == DEPR::LOW
198 }
199}
200#[doc = "Possible values of the field `DEM`"]
201#[derive(Clone, Copy, Debug, PartialEq)]
202pub enum DEMR {
203 #[doc = "DE function is disabled"]
204 DISABLED,
205 #[doc = "The DE signal is output on the RTS pin"]
206 ENABLED,
207}
208impl DEMR {
209 #[doc = r" Returns `true` if the bit is clear (0)"]
210 #[inline]
211 pub fn bit_is_clear(&self) -> bool {
212 !self.bit()
213 }
214 #[doc = r" Returns `true` if the bit is set (1)"]
215 #[inline]
216 pub fn bit_is_set(&self) -> bool {
217 self.bit()
218 }
219 #[doc = r" Value of the field as raw bits"]
220 #[inline]
221 pub fn bit(&self) -> bool {
222 match *self {
223 DEMR::DISABLED => false,
224 DEMR::ENABLED => true,
225 }
226 }
227 #[allow(missing_docs)]
228 #[doc(hidden)]
229 #[inline]
230 pub fn _from(value: bool) -> DEMR {
231 match value {
232 false => DEMR::DISABLED,
233 true => DEMR::ENABLED,
234 }
235 }
236 #[doc = "Checks if the value of the field is `DISABLED`"]
237 #[inline]
238 pub fn is_disabled(&self) -> bool {
239 *self == DEMR::DISABLED
240 }
241 #[doc = "Checks if the value of the field is `ENABLED`"]
242 #[inline]
243 pub fn is_enabled(&self) -> bool {
244 *self == DEMR::ENABLED
245 }
246}
247#[doc = "Possible values of the field `DDRE`"]
248#[derive(Clone, Copy, Debug, PartialEq)]
249pub enum DDRER {
250 #[doc = "DMA is not disabled in case of reception error"]
251 NOTDISABLED,
252 #[doc = "DMA is disabled following a reception error"]
253 DISABLED,
254}
255impl DDRER {
256 #[doc = r" Returns `true` if the bit is clear (0)"]
257 #[inline]
258 pub fn bit_is_clear(&self) -> bool {
259 !self.bit()
260 }
261 #[doc = r" Returns `true` if the bit is set (1)"]
262 #[inline]
263 pub fn bit_is_set(&self) -> bool {
264 self.bit()
265 }
266 #[doc = r" Value of the field as raw bits"]
267 #[inline]
268 pub fn bit(&self) -> bool {
269 match *self {
270 DDRER::NOTDISABLED => false,
271 DDRER::DISABLED => true,
272 }
273 }
274 #[allow(missing_docs)]
275 #[doc(hidden)]
276 #[inline]
277 pub fn _from(value: bool) -> DDRER {
278 match value {
279 false => DDRER::NOTDISABLED,
280 true => DDRER::DISABLED,
281 }
282 }
283 #[doc = "Checks if the value of the field is `NOTDISABLED`"]
284 #[inline]
285 pub fn is_not_disabled(&self) -> bool {
286 *self == DDRER::NOTDISABLED
287 }
288 #[doc = "Checks if the value of the field is `DISABLED`"]
289 #[inline]
290 pub fn is_disabled(&self) -> bool {
291 *self == DDRER::DISABLED
292 }
293}
294#[doc = "Possible values of the field `OVRDIS`"]
295#[derive(Clone, Copy, Debug, PartialEq)]
296pub enum OVRDISR {
297 #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
298 ENABLED,
299 #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
300 DISABLED,
301}
302impl OVRDISR {
303 #[doc = r" Returns `true` if the bit is clear (0)"]
304 #[inline]
305 pub fn bit_is_clear(&self) -> bool {
306 !self.bit()
307 }
308 #[doc = r" Returns `true` if the bit is set (1)"]
309 #[inline]
310 pub fn bit_is_set(&self) -> bool {
311 self.bit()
312 }
313 #[doc = r" Value of the field as raw bits"]
314 #[inline]
315 pub fn bit(&self) -> bool {
316 match *self {
317 OVRDISR::ENABLED => false,
318 OVRDISR::DISABLED => true,
319 }
320 }
321 #[allow(missing_docs)]
322 #[doc(hidden)]
323 #[inline]
324 pub fn _from(value: bool) -> OVRDISR {
325 match value {
326 false => OVRDISR::ENABLED,
327 true => OVRDISR::DISABLED,
328 }
329 }
330 #[doc = "Checks if the value of the field is `ENABLED`"]
331 #[inline]
332 pub fn is_enabled(&self) -> bool {
333 *self == OVRDISR::ENABLED
334 }
335 #[doc = "Checks if the value of the field is `DISABLED`"]
336 #[inline]
337 pub fn is_disabled(&self) -> bool {
338 *self == OVRDISR::DISABLED
339 }
340}
341#[doc = "Possible values of the field `ONEBIT`"]
342#[derive(Clone, Copy, Debug, PartialEq)]
343pub enum ONEBITR {
344 #[doc = "Three sample bit method"]
345 SAMPLE3,
346 #[doc = "One sample bit method"]
347 SAMPLE1,
348}
349impl ONEBITR {
350 #[doc = r" Returns `true` if the bit is clear (0)"]
351 #[inline]
352 pub fn bit_is_clear(&self) -> bool {
353 !self.bit()
354 }
355 #[doc = r" Returns `true` if the bit is set (1)"]
356 #[inline]
357 pub fn bit_is_set(&self) -> bool {
358 self.bit()
359 }
360 #[doc = r" Value of the field as raw bits"]
361 #[inline]
362 pub fn bit(&self) -> bool {
363 match *self {
364 ONEBITR::SAMPLE3 => false,
365 ONEBITR::SAMPLE1 => true,
366 }
367 }
368 #[allow(missing_docs)]
369 #[doc(hidden)]
370 #[inline]
371 pub fn _from(value: bool) -> ONEBITR {
372 match value {
373 false => ONEBITR::SAMPLE3,
374 true => ONEBITR::SAMPLE1,
375 }
376 }
377 #[doc = "Checks if the value of the field is `SAMPLE3`"]
378 #[inline]
379 pub fn is_sample3(&self) -> bool {
380 *self == ONEBITR::SAMPLE3
381 }
382 #[doc = "Checks if the value of the field is `SAMPLE1`"]
383 #[inline]
384 pub fn is_sample1(&self) -> bool {
385 *self == ONEBITR::SAMPLE1
386 }
387}
388#[doc = "Possible values of the field `CTSIE`"]
389#[derive(Clone, Copy, Debug, PartialEq)]
390pub enum CTSIER {
391 #[doc = "Interrupt is inhibited"]
392 DISABLED,
393 #[doc = "An interrupt is generated whenever CTSIF=1 in the ISR register"]
394 ENABLED,
395}
396impl CTSIER {
397 #[doc = r" Returns `true` if the bit is clear (0)"]
398 #[inline]
399 pub fn bit_is_clear(&self) -> bool {
400 !self.bit()
401 }
402 #[doc = r" Returns `true` if the bit is set (1)"]
403 #[inline]
404 pub fn bit_is_set(&self) -> bool {
405 self.bit()
406 }
407 #[doc = r" Value of the field as raw bits"]
408 #[inline]
409 pub fn bit(&self) -> bool {
410 match *self {
411 CTSIER::DISABLED => false,
412 CTSIER::ENABLED => true,
413 }
414 }
415 #[allow(missing_docs)]
416 #[doc(hidden)]
417 #[inline]
418 pub fn _from(value: bool) -> CTSIER {
419 match value {
420 false => CTSIER::DISABLED,
421 true => CTSIER::ENABLED,
422 }
423 }
424 #[doc = "Checks if the value of the field is `DISABLED`"]
425 #[inline]
426 pub fn is_disabled(&self) -> bool {
427 *self == CTSIER::DISABLED
428 }
429 #[doc = "Checks if the value of the field is `ENABLED`"]
430 #[inline]
431 pub fn is_enabled(&self) -> bool {
432 *self == CTSIER::ENABLED
433 }
434}
435#[doc = "Possible values of the field `CTSE`"]
436#[derive(Clone, Copy, Debug, PartialEq)]
437pub enum CTSER {
438 #[doc = "CTS hardware flow control disabled"]
439 DISABLED,
440 #[doc = "CTS mode enabled, data is only transmitted when the CTS input is asserted"]
441 ENABLED,
442}
443impl CTSER {
444 #[doc = r" Returns `true` if the bit is clear (0)"]
445 #[inline]
446 pub fn bit_is_clear(&self) -> bool {
447 !self.bit()
448 }
449 #[doc = r" Returns `true` if the bit is set (1)"]
450 #[inline]
451 pub fn bit_is_set(&self) -> bool {
452 self.bit()
453 }
454 #[doc = r" Value of the field as raw bits"]
455 #[inline]
456 pub fn bit(&self) -> bool {
457 match *self {
458 CTSER::DISABLED => false,
459 CTSER::ENABLED => true,
460 }
461 }
462 #[allow(missing_docs)]
463 #[doc(hidden)]
464 #[inline]
465 pub fn _from(value: bool) -> CTSER {
466 match value {
467 false => CTSER::DISABLED,
468 true => CTSER::ENABLED,
469 }
470 }
471 #[doc = "Checks if the value of the field is `DISABLED`"]
472 #[inline]
473 pub fn is_disabled(&self) -> bool {
474 *self == CTSER::DISABLED
475 }
476 #[doc = "Checks if the value of the field is `ENABLED`"]
477 #[inline]
478 pub fn is_enabled(&self) -> bool {
479 *self == CTSER::ENABLED
480 }
481}
482#[doc = "Possible values of the field `RTSE`"]
483#[derive(Clone, Copy, Debug, PartialEq)]
484pub enum RTSER {
485 #[doc = "RTS hardware flow control disabled"]
486 DISABLED,
487 #[doc = "RTS output enabled, data is only requested when there is space in the receive buffer"]
488 ENABLED,
489}
490impl RTSER {
491 #[doc = r" Returns `true` if the bit is clear (0)"]
492 #[inline]
493 pub fn bit_is_clear(&self) -> bool {
494 !self.bit()
495 }
496 #[doc = r" Returns `true` if the bit is set (1)"]
497 #[inline]
498 pub fn bit_is_set(&self) -> bool {
499 self.bit()
500 }
501 #[doc = r" Value of the field as raw bits"]
502 #[inline]
503 pub fn bit(&self) -> bool {
504 match *self {
505 RTSER::DISABLED => false,
506 RTSER::ENABLED => true,
507 }
508 }
509 #[allow(missing_docs)]
510 #[doc(hidden)]
511 #[inline]
512 pub fn _from(value: bool) -> RTSER {
513 match value {
514 false => RTSER::DISABLED,
515 true => RTSER::ENABLED,
516 }
517 }
518 #[doc = "Checks if the value of the field is `DISABLED`"]
519 #[inline]
520 pub fn is_disabled(&self) -> bool {
521 *self == RTSER::DISABLED
522 }
523 #[doc = "Checks if the value of the field is `ENABLED`"]
524 #[inline]
525 pub fn is_enabled(&self) -> bool {
526 *self == RTSER::ENABLED
527 }
528}
529#[doc = "Possible values of the field `DMAT`"]
530#[derive(Clone, Copy, Debug, PartialEq)]
531pub enum DMATR {
532 #[doc = "DMA mode is disabled for transmission"]
533 DISABLED,
534 #[doc = "DMA mode is enabled for transmission"]
535 ENABLED,
536}
537impl DMATR {
538 #[doc = r" Returns `true` if the bit is clear (0)"]
539 #[inline]
540 pub fn bit_is_clear(&self) -> bool {
541 !self.bit()
542 }
543 #[doc = r" Returns `true` if the bit is set (1)"]
544 #[inline]
545 pub fn bit_is_set(&self) -> bool {
546 self.bit()
547 }
548 #[doc = r" Value of the field as raw bits"]
549 #[inline]
550 pub fn bit(&self) -> bool {
551 match *self {
552 DMATR::DISABLED => false,
553 DMATR::ENABLED => true,
554 }
555 }
556 #[allow(missing_docs)]
557 #[doc(hidden)]
558 #[inline]
559 pub fn _from(value: bool) -> DMATR {
560 match value {
561 false => DMATR::DISABLED,
562 true => DMATR::ENABLED,
563 }
564 }
565 #[doc = "Checks if the value of the field is `DISABLED`"]
566 #[inline]
567 pub fn is_disabled(&self) -> bool {
568 *self == DMATR::DISABLED
569 }
570 #[doc = "Checks if the value of the field is `ENABLED`"]
571 #[inline]
572 pub fn is_enabled(&self) -> bool {
573 *self == DMATR::ENABLED
574 }
575}
576#[doc = "Possible values of the field `DMAR`"]
577#[derive(Clone, Copy, Debug, PartialEq)]
578pub enum DMARR {
579 #[doc = "DMA mode is disabled for reception"]
580 DISABLED,
581 #[doc = "DMA mode is enabled for reception"]
582 ENABLED,
583}
584impl DMARR {
585 #[doc = r" Returns `true` if the bit is clear (0)"]
586 #[inline]
587 pub fn bit_is_clear(&self) -> bool {
588 !self.bit()
589 }
590 #[doc = r" Returns `true` if the bit is set (1)"]
591 #[inline]
592 pub fn bit_is_set(&self) -> bool {
593 self.bit()
594 }
595 #[doc = r" Value of the field as raw bits"]
596 #[inline]
597 pub fn bit(&self) -> bool {
598 match *self {
599 DMARR::DISABLED => false,
600 DMARR::ENABLED => true,
601 }
602 }
603 #[allow(missing_docs)]
604 #[doc(hidden)]
605 #[inline]
606 pub fn _from(value: bool) -> DMARR {
607 match value {
608 false => DMARR::DISABLED,
609 true => DMARR::ENABLED,
610 }
611 }
612 #[doc = "Checks if the value of the field is `DISABLED`"]
613 #[inline]
614 pub fn is_disabled(&self) -> bool {
615 *self == DMARR::DISABLED
616 }
617 #[doc = "Checks if the value of the field is `ENABLED`"]
618 #[inline]
619 pub fn is_enabled(&self) -> bool {
620 *self == DMARR::ENABLED
621 }
622}
623#[doc = "Possible values of the field `SCEN`"]
624#[derive(Clone, Copy, Debug, PartialEq)]
625pub enum SCENR {
626 #[doc = "Smartcard Mode disabled"]
627 DISABLED,
628 #[doc = "Smartcard Mode enabled"]
629 ENABLED,
630}
631impl SCENR {
632 #[doc = r" Returns `true` if the bit is clear (0)"]
633 #[inline]
634 pub fn bit_is_clear(&self) -> bool {
635 !self.bit()
636 }
637 #[doc = r" Returns `true` if the bit is set (1)"]
638 #[inline]
639 pub fn bit_is_set(&self) -> bool {
640 self.bit()
641 }
642 #[doc = r" Value of the field as raw bits"]
643 #[inline]
644 pub fn bit(&self) -> bool {
645 match *self {
646 SCENR::DISABLED => false,
647 SCENR::ENABLED => true,
648 }
649 }
650 #[allow(missing_docs)]
651 #[doc(hidden)]
652 #[inline]
653 pub fn _from(value: bool) -> SCENR {
654 match value {
655 false => SCENR::DISABLED,
656 true => SCENR::ENABLED,
657 }
658 }
659 #[doc = "Checks if the value of the field is `DISABLED`"]
660 #[inline]
661 pub fn is_disabled(&self) -> bool {
662 *self == SCENR::DISABLED
663 }
664 #[doc = "Checks if the value of the field is `ENABLED`"]
665 #[inline]
666 pub fn is_enabled(&self) -> bool {
667 *self == SCENR::ENABLED
668 }
669}
670#[doc = "Possible values of the field `NACK`"]
671#[derive(Clone, Copy, Debug, PartialEq)]
672pub enum NACKR {
673 #[doc = "NACK transmission in case of parity error is disabled"]
674 DISABLED,
675 #[doc = "NACK transmission during parity error is enabled"]
676 ENABLED,
677}
678impl NACKR {
679 #[doc = r" Returns `true` if the bit is clear (0)"]
680 #[inline]
681 pub fn bit_is_clear(&self) -> bool {
682 !self.bit()
683 }
684 #[doc = r" Returns `true` if the bit is set (1)"]
685 #[inline]
686 pub fn bit_is_set(&self) -> bool {
687 self.bit()
688 }
689 #[doc = r" Value of the field as raw bits"]
690 #[inline]
691 pub fn bit(&self) -> bool {
692 match *self {
693 NACKR::DISABLED => false,
694 NACKR::ENABLED => true,
695 }
696 }
697 #[allow(missing_docs)]
698 #[doc(hidden)]
699 #[inline]
700 pub fn _from(value: bool) -> NACKR {
701 match value {
702 false => NACKR::DISABLED,
703 true => NACKR::ENABLED,
704 }
705 }
706 #[doc = "Checks if the value of the field is `DISABLED`"]
707 #[inline]
708 pub fn is_disabled(&self) -> bool {
709 *self == NACKR::DISABLED
710 }
711 #[doc = "Checks if the value of the field is `ENABLED`"]
712 #[inline]
713 pub fn is_enabled(&self) -> bool {
714 *self == NACKR::ENABLED
715 }
716}
717#[doc = "Possible values of the field `HDSEL`"]
718#[derive(Clone, Copy, Debug, PartialEq)]
719pub enum HDSELR {
720 #[doc = "Half duplex mode is not selected"]
721 NOTSELECTED,
722 #[doc = "Half duplex mode is selected"]
723 SELECTED,
724}
725impl HDSELR {
726 #[doc = r" Returns `true` if the bit is clear (0)"]
727 #[inline]
728 pub fn bit_is_clear(&self) -> bool {
729 !self.bit()
730 }
731 #[doc = r" Returns `true` if the bit is set (1)"]
732 #[inline]
733 pub fn bit_is_set(&self) -> bool {
734 self.bit()
735 }
736 #[doc = r" Value of the field as raw bits"]
737 #[inline]
738 pub fn bit(&self) -> bool {
739 match *self {
740 HDSELR::NOTSELECTED => false,
741 HDSELR::SELECTED => true,
742 }
743 }
744 #[allow(missing_docs)]
745 #[doc(hidden)]
746 #[inline]
747 pub fn _from(value: bool) -> HDSELR {
748 match value {
749 false => HDSELR::NOTSELECTED,
750 true => HDSELR::SELECTED,
751 }
752 }
753 #[doc = "Checks if the value of the field is `NOTSELECTED`"]
754 #[inline]
755 pub fn is_not_selected(&self) -> bool {
756 *self == HDSELR::NOTSELECTED
757 }
758 #[doc = "Checks if the value of the field is `SELECTED`"]
759 #[inline]
760 pub fn is_selected(&self) -> bool {
761 *self == HDSELR::SELECTED
762 }
763}
764#[doc = "Possible values of the field `IRLP`"]
765#[derive(Clone, Copy, Debug, PartialEq)]
766pub enum IRLPR {
767 #[doc = "Normal mode"]
768 NORMAL,
769 #[doc = "Low-power mode"]
770 LOWPOWER,
771}
772impl IRLPR {
773 #[doc = r" Returns `true` if the bit is clear (0)"]
774 #[inline]
775 pub fn bit_is_clear(&self) -> bool {
776 !self.bit()
777 }
778 #[doc = r" Returns `true` if the bit is set (1)"]
779 #[inline]
780 pub fn bit_is_set(&self) -> bool {
781 self.bit()
782 }
783 #[doc = r" Value of the field as raw bits"]
784 #[inline]
785 pub fn bit(&self) -> bool {
786 match *self {
787 IRLPR::NORMAL => false,
788 IRLPR::LOWPOWER => true,
789 }
790 }
791 #[allow(missing_docs)]
792 #[doc(hidden)]
793 #[inline]
794 pub fn _from(value: bool) -> IRLPR {
795 match value {
796 false => IRLPR::NORMAL,
797 true => IRLPR::LOWPOWER,
798 }
799 }
800 #[doc = "Checks if the value of the field is `NORMAL`"]
801 #[inline]
802 pub fn is_normal(&self) -> bool {
803 *self == IRLPR::NORMAL
804 }
805 #[doc = "Checks if the value of the field is `LOWPOWER`"]
806 #[inline]
807 pub fn is_low_power(&self) -> bool {
808 *self == IRLPR::LOWPOWER
809 }
810}
811#[doc = "Possible values of the field `IREN`"]
812#[derive(Clone, Copy, Debug, PartialEq)]
813pub enum IRENR {
814 #[doc = "IrDA disabled"]
815 DISABLED,
816 #[doc = "IrDA enabled"]
817 ENABLED,
818}
819impl IRENR {
820 #[doc = r" Returns `true` if the bit is clear (0)"]
821 #[inline]
822 pub fn bit_is_clear(&self) -> bool {
823 !self.bit()
824 }
825 #[doc = r" Returns `true` if the bit is set (1)"]
826 #[inline]
827 pub fn bit_is_set(&self) -> bool {
828 self.bit()
829 }
830 #[doc = r" Value of the field as raw bits"]
831 #[inline]
832 pub fn bit(&self) -> bool {
833 match *self {
834 IRENR::DISABLED => false,
835 IRENR::ENABLED => true,
836 }
837 }
838 #[allow(missing_docs)]
839 #[doc(hidden)]
840 #[inline]
841 pub fn _from(value: bool) -> IRENR {
842 match value {
843 false => IRENR::DISABLED,
844 true => IRENR::ENABLED,
845 }
846 }
847 #[doc = "Checks if the value of the field is `DISABLED`"]
848 #[inline]
849 pub fn is_disabled(&self) -> bool {
850 *self == IRENR::DISABLED
851 }
852 #[doc = "Checks if the value of the field is `ENABLED`"]
853 #[inline]
854 pub fn is_enabled(&self) -> bool {
855 *self == IRENR::ENABLED
856 }
857}
858#[doc = "Possible values of the field `EIE`"]
859#[derive(Clone, Copy, Debug, PartialEq)]
860pub enum EIER {
861 #[doc = "Interrupt is inhibited"]
862 DISABLED,
863 #[doc = "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"]
864 ENABLED,
865}
866impl EIER {
867 #[doc = r" Returns `true` if the bit is clear (0)"]
868 #[inline]
869 pub fn bit_is_clear(&self) -> bool {
870 !self.bit()
871 }
872 #[doc = r" Returns `true` if the bit is set (1)"]
873 #[inline]
874 pub fn bit_is_set(&self) -> bool {
875 self.bit()
876 }
877 #[doc = r" Value of the field as raw bits"]
878 #[inline]
879 pub fn bit(&self) -> bool {
880 match *self {
881 EIER::DISABLED => false,
882 EIER::ENABLED => true,
883 }
884 }
885 #[allow(missing_docs)]
886 #[doc(hidden)]
887 #[inline]
888 pub fn _from(value: bool) -> EIER {
889 match value {
890 false => EIER::DISABLED,
891 true => EIER::ENABLED,
892 }
893 }
894 #[doc = "Checks if the value of the field is `DISABLED`"]
895 #[inline]
896 pub fn is_disabled(&self) -> bool {
897 *self == EIER::DISABLED
898 }
899 #[doc = "Checks if the value of the field is `ENABLED`"]
900 #[inline]
901 pub fn is_enabled(&self) -> bool {
902 *self == EIER::ENABLED
903 }
904}
905#[doc = "Values that can be written to the field `WUFIE`"]
906pub enum WUFIEW {
907 #[doc = "Interrupt is inhibited"]
908 DISABLED,
909 #[doc = "An USART interrupt is generated whenever WUF=1 in the ISR register"]
910 ENABLED,
911}
912impl WUFIEW {
913 #[allow(missing_docs)]
914 #[doc(hidden)]
915 #[inline]
916 pub fn _bits(&self) -> bool {
917 match *self {
918 WUFIEW::DISABLED => false,
919 WUFIEW::ENABLED => true,
920 }
921 }
922}
923#[doc = r" Proxy"]
924pub struct _WUFIEW<'a> {
925 w: &'a mut W,
926}
927impl<'a> _WUFIEW<'a> {
928 #[doc = r" Writes `variant` to the field"]
929 #[inline]
930 pub fn variant(self, variant: WUFIEW) -> &'a mut W {
931 {
932 self.bit(variant._bits())
933 }
934 }
935 #[doc = "Interrupt is inhibited"]
936 #[inline]
937 pub fn disabled(self) -> &'a mut W {
938 self.variant(WUFIEW::DISABLED)
939 }
940 #[doc = "An USART interrupt is generated whenever WUF=1 in the ISR register"]
941 #[inline]
942 pub fn enabled(self) -> &'a mut W {
943 self.variant(WUFIEW::ENABLED)
944 }
945 #[doc = r" Sets the field bit"]
946 pub fn set_bit(self) -> &'a mut W {
947 self.bit(true)
948 }
949 #[doc = r" Clears the field bit"]
950 pub fn clear_bit(self) -> &'a mut W {
951 self.bit(false)
952 }
953 #[doc = r" Writes raw bits to the field"]
954 #[inline]
955 pub fn bit(self, value: bool) -> &'a mut W {
956 const MASK: bool = true;
957 const OFFSET: u8 = 22;
958 self.w.bits &= !((MASK as u32) << OFFSET);
959 self.w.bits |= ((value & MASK) as u32) << OFFSET;
960 self.w
961 }
962}
963#[doc = "Values that can be written to the field `WUS`"]
964pub enum WUSW {
965 #[doc = "WUF active on address match"]
966 ADDRESS,
967 #[doc = "WuF active on Start bit detection"]
968 START,
969 #[doc = "WUF active on RXNE"]
970 RXNE,
971}
972impl WUSW {
973 #[allow(missing_docs)]
974 #[doc(hidden)]
975 #[inline]
976 pub fn _bits(&self) -> u8 {
977 match *self {
978 WUSW::ADDRESS => 0,
979 WUSW::START => 2,
980 WUSW::RXNE => 3,
981 }
982 }
983}
984#[doc = r" Proxy"]
985pub struct _WUSW<'a> {
986 w: &'a mut W,
987}
988impl<'a> _WUSW<'a> {
989 #[doc = r" Writes `variant` to the field"]
990 #[inline]
991 pub fn variant(self, variant: WUSW) -> &'a mut W {
992 unsafe { self.bits(variant._bits()) }
993 }
994 #[doc = "WUF active on address match"]
995 #[inline]
996 pub fn address(self) -> &'a mut W {
997 self.variant(WUSW::ADDRESS)
998 }
999 #[doc = "WuF active on Start bit detection"]
1000 #[inline]
1001 pub fn start(self) -> &'a mut W {
1002 self.variant(WUSW::START)
1003 }
1004 #[doc = "WUF active on RXNE"]
1005 #[inline]
1006 pub fn rxne(self) -> &'a mut W {
1007 self.variant(WUSW::RXNE)
1008 }
1009 #[doc = r" Writes raw bits to the field"]
1010 #[inline]
1011 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1012 const MASK: u8 = 3;
1013 const OFFSET: u8 = 20;
1014 self.w.bits &= !((MASK as u32) << OFFSET);
1015 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1016 self.w
1017 }
1018}
1019#[doc = r" Proxy"]
1020pub struct _SCARCNTW<'a> {
1021 w: &'a mut W,
1022}
1023impl<'a> _SCARCNTW<'a> {
1024 #[doc = r" Writes raw bits to the field"]
1025 #[inline]
1026 pub fn bits(self, value: u8) -> &'a mut W {
1027 const MASK: u8 = 7;
1028 const OFFSET: u8 = 17;
1029 self.w.bits &= !((MASK as u32) << OFFSET);
1030 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1031 self.w
1032 }
1033}
1034#[doc = "Values that can be written to the field `DEP`"]
1035pub enum DEPW {
1036 #[doc = "DE signal is active high"]
1037 HIGH,
1038 #[doc = "DE signal is active low"]
1039 LOW,
1040}
1041impl DEPW {
1042 #[allow(missing_docs)]
1043 #[doc(hidden)]
1044 #[inline]
1045 pub fn _bits(&self) -> bool {
1046 match *self {
1047 DEPW::HIGH => false,
1048 DEPW::LOW => true,
1049 }
1050 }
1051}
1052#[doc = r" Proxy"]
1053pub struct _DEPW<'a> {
1054 w: &'a mut W,
1055}
1056impl<'a> _DEPW<'a> {
1057 #[doc = r" Writes `variant` to the field"]
1058 #[inline]
1059 pub fn variant(self, variant: DEPW) -> &'a mut W {
1060 {
1061 self.bit(variant._bits())
1062 }
1063 }
1064 #[doc = "DE signal is active high"]
1065 #[inline]
1066 pub fn high(self) -> &'a mut W {
1067 self.variant(DEPW::HIGH)
1068 }
1069 #[doc = "DE signal is active low"]
1070 #[inline]
1071 pub fn low(self) -> &'a mut W {
1072 self.variant(DEPW::LOW)
1073 }
1074 #[doc = r" Sets the field bit"]
1075 pub fn set_bit(self) -> &'a mut W {
1076 self.bit(true)
1077 }
1078 #[doc = r" Clears the field bit"]
1079 pub fn clear_bit(self) -> &'a mut W {
1080 self.bit(false)
1081 }
1082 #[doc = r" Writes raw bits to the field"]
1083 #[inline]
1084 pub fn bit(self, value: bool) -> &'a mut W {
1085 const MASK: bool = true;
1086 const OFFSET: u8 = 15;
1087 self.w.bits &= !((MASK as u32) << OFFSET);
1088 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1089 self.w
1090 }
1091}
1092#[doc = "Values that can be written to the field `DEM`"]
1093pub enum DEMW {
1094 #[doc = "DE function is disabled"]
1095 DISABLED,
1096 #[doc = "The DE signal is output on the RTS pin"]
1097 ENABLED,
1098}
1099impl DEMW {
1100 #[allow(missing_docs)]
1101 #[doc(hidden)]
1102 #[inline]
1103 pub fn _bits(&self) -> bool {
1104 match *self {
1105 DEMW::DISABLED => false,
1106 DEMW::ENABLED => true,
1107 }
1108 }
1109}
1110#[doc = r" Proxy"]
1111pub struct _DEMW<'a> {
1112 w: &'a mut W,
1113}
1114impl<'a> _DEMW<'a> {
1115 #[doc = r" Writes `variant` to the field"]
1116 #[inline]
1117 pub fn variant(self, variant: DEMW) -> &'a mut W {
1118 {
1119 self.bit(variant._bits())
1120 }
1121 }
1122 #[doc = "DE function is disabled"]
1123 #[inline]
1124 pub fn disabled(self) -> &'a mut W {
1125 self.variant(DEMW::DISABLED)
1126 }
1127 #[doc = "The DE signal is output on the RTS pin"]
1128 #[inline]
1129 pub fn enabled(self) -> &'a mut W {
1130 self.variant(DEMW::ENABLED)
1131 }
1132 #[doc = r" Sets the field bit"]
1133 pub fn set_bit(self) -> &'a mut W {
1134 self.bit(true)
1135 }
1136 #[doc = r" Clears the field bit"]
1137 pub fn clear_bit(self) -> &'a mut W {
1138 self.bit(false)
1139 }
1140 #[doc = r" Writes raw bits to the field"]
1141 #[inline]
1142 pub fn bit(self, value: bool) -> &'a mut W {
1143 const MASK: bool = true;
1144 const OFFSET: u8 = 14;
1145 self.w.bits &= !((MASK as u32) << OFFSET);
1146 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1147 self.w
1148 }
1149}
1150#[doc = "Values that can be written to the field `DDRE`"]
1151pub enum DDREW {
1152 #[doc = "DMA is not disabled in case of reception error"]
1153 NOTDISABLED,
1154 #[doc = "DMA is disabled following a reception error"]
1155 DISABLED,
1156}
1157impl DDREW {
1158 #[allow(missing_docs)]
1159 #[doc(hidden)]
1160 #[inline]
1161 pub fn _bits(&self) -> bool {
1162 match *self {
1163 DDREW::NOTDISABLED => false,
1164 DDREW::DISABLED => true,
1165 }
1166 }
1167}
1168#[doc = r" Proxy"]
1169pub struct _DDREW<'a> {
1170 w: &'a mut W,
1171}
1172impl<'a> _DDREW<'a> {
1173 #[doc = r" Writes `variant` to the field"]
1174 #[inline]
1175 pub fn variant(self, variant: DDREW) -> &'a mut W {
1176 {
1177 self.bit(variant._bits())
1178 }
1179 }
1180 #[doc = "DMA is not disabled in case of reception error"]
1181 #[inline]
1182 pub fn not_disabled(self) -> &'a mut W {
1183 self.variant(DDREW::NOTDISABLED)
1184 }
1185 #[doc = "DMA is disabled following a reception error"]
1186 #[inline]
1187 pub fn disabled(self) -> &'a mut W {
1188 self.variant(DDREW::DISABLED)
1189 }
1190 #[doc = r" Sets the field bit"]
1191 pub fn set_bit(self) -> &'a mut W {
1192 self.bit(true)
1193 }
1194 #[doc = r" Clears the field bit"]
1195 pub fn clear_bit(self) -> &'a mut W {
1196 self.bit(false)
1197 }
1198 #[doc = r" Writes raw bits to the field"]
1199 #[inline]
1200 pub fn bit(self, value: bool) -> &'a mut W {
1201 const MASK: bool = true;
1202 const OFFSET: u8 = 13;
1203 self.w.bits &= !((MASK as u32) << OFFSET);
1204 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1205 self.w
1206 }
1207}
1208#[doc = "Values that can be written to the field `OVRDIS`"]
1209pub enum OVRDISW {
1210 #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
1211 ENABLED,
1212 #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
1213 DISABLED,
1214}
1215impl OVRDISW {
1216 #[allow(missing_docs)]
1217 #[doc(hidden)]
1218 #[inline]
1219 pub fn _bits(&self) -> bool {
1220 match *self {
1221 OVRDISW::ENABLED => false,
1222 OVRDISW::DISABLED => true,
1223 }
1224 }
1225}
1226#[doc = r" Proxy"]
1227pub struct _OVRDISW<'a> {
1228 w: &'a mut W,
1229}
1230impl<'a> _OVRDISW<'a> {
1231 #[doc = r" Writes `variant` to the field"]
1232 #[inline]
1233 pub fn variant(self, variant: OVRDISW) -> &'a mut W {
1234 {
1235 self.bit(variant._bits())
1236 }
1237 }
1238 #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
1239 #[inline]
1240 pub fn enabled(self) -> &'a mut W {
1241 self.variant(OVRDISW::ENABLED)
1242 }
1243 #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
1244 #[inline]
1245 pub fn disabled(self) -> &'a mut W {
1246 self.variant(OVRDISW::DISABLED)
1247 }
1248 #[doc = r" Sets the field bit"]
1249 pub fn set_bit(self) -> &'a mut W {
1250 self.bit(true)
1251 }
1252 #[doc = r" Clears the field bit"]
1253 pub fn clear_bit(self) -> &'a mut W {
1254 self.bit(false)
1255 }
1256 #[doc = r" Writes raw bits to the field"]
1257 #[inline]
1258 pub fn bit(self, value: bool) -> &'a mut W {
1259 const MASK: bool = true;
1260 const OFFSET: u8 = 12;
1261 self.w.bits &= !((MASK as u32) << OFFSET);
1262 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1263 self.w
1264 }
1265}
1266#[doc = "Values that can be written to the field `ONEBIT`"]
1267pub enum ONEBITW {
1268 #[doc = "Three sample bit method"]
1269 SAMPLE3,
1270 #[doc = "One sample bit method"]
1271 SAMPLE1,
1272}
1273impl ONEBITW {
1274 #[allow(missing_docs)]
1275 #[doc(hidden)]
1276 #[inline]
1277 pub fn _bits(&self) -> bool {
1278 match *self {
1279 ONEBITW::SAMPLE3 => false,
1280 ONEBITW::SAMPLE1 => true,
1281 }
1282 }
1283}
1284#[doc = r" Proxy"]
1285pub struct _ONEBITW<'a> {
1286 w: &'a mut W,
1287}
1288impl<'a> _ONEBITW<'a> {
1289 #[doc = r" Writes `variant` to the field"]
1290 #[inline]
1291 pub fn variant(self, variant: ONEBITW) -> &'a mut W {
1292 {
1293 self.bit(variant._bits())
1294 }
1295 }
1296 #[doc = "Three sample bit method"]
1297 #[inline]
1298 pub fn sample3(self) -> &'a mut W {
1299 self.variant(ONEBITW::SAMPLE3)
1300 }
1301 #[doc = "One sample bit method"]
1302 #[inline]
1303 pub fn sample1(self) -> &'a mut W {
1304 self.variant(ONEBITW::SAMPLE1)
1305 }
1306 #[doc = r" Sets the field bit"]
1307 pub fn set_bit(self) -> &'a mut W {
1308 self.bit(true)
1309 }
1310 #[doc = r" Clears the field bit"]
1311 pub fn clear_bit(self) -> &'a mut W {
1312 self.bit(false)
1313 }
1314 #[doc = r" Writes raw bits to the field"]
1315 #[inline]
1316 pub fn bit(self, value: bool) -> &'a mut W {
1317 const MASK: bool = true;
1318 const OFFSET: u8 = 11;
1319 self.w.bits &= !((MASK as u32) << OFFSET);
1320 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1321 self.w
1322 }
1323}
1324#[doc = "Values that can be written to the field `CTSIE`"]
1325pub enum CTSIEW {
1326 #[doc = "Interrupt is inhibited"]
1327 DISABLED,
1328 #[doc = "An interrupt is generated whenever CTSIF=1 in the ISR register"]
1329 ENABLED,
1330}
1331impl CTSIEW {
1332 #[allow(missing_docs)]
1333 #[doc(hidden)]
1334 #[inline]
1335 pub fn _bits(&self) -> bool {
1336 match *self {
1337 CTSIEW::DISABLED => false,
1338 CTSIEW::ENABLED => true,
1339 }
1340 }
1341}
1342#[doc = r" Proxy"]
1343pub struct _CTSIEW<'a> {
1344 w: &'a mut W,
1345}
1346impl<'a> _CTSIEW<'a> {
1347 #[doc = r" Writes `variant` to the field"]
1348 #[inline]
1349 pub fn variant(self, variant: CTSIEW) -> &'a mut W {
1350 {
1351 self.bit(variant._bits())
1352 }
1353 }
1354 #[doc = "Interrupt is inhibited"]
1355 #[inline]
1356 pub fn disabled(self) -> &'a mut W {
1357 self.variant(CTSIEW::DISABLED)
1358 }
1359 #[doc = "An interrupt is generated whenever CTSIF=1 in the ISR register"]
1360 #[inline]
1361 pub fn enabled(self) -> &'a mut W {
1362 self.variant(CTSIEW::ENABLED)
1363 }
1364 #[doc = r" Sets the field bit"]
1365 pub fn set_bit(self) -> &'a mut W {
1366 self.bit(true)
1367 }
1368 #[doc = r" Clears the field bit"]
1369 pub fn clear_bit(self) -> &'a mut W {
1370 self.bit(false)
1371 }
1372 #[doc = r" Writes raw bits to the field"]
1373 #[inline]
1374 pub fn bit(self, value: bool) -> &'a mut W {
1375 const MASK: bool = true;
1376 const OFFSET: u8 = 10;
1377 self.w.bits &= !((MASK as u32) << OFFSET);
1378 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1379 self.w
1380 }
1381}
1382#[doc = "Values that can be written to the field `CTSE`"]
1383pub enum CTSEW {
1384 #[doc = "CTS hardware flow control disabled"]
1385 DISABLED,
1386 #[doc = "CTS mode enabled, data is only transmitted when the CTS input is asserted"]
1387 ENABLED,
1388}
1389impl CTSEW {
1390 #[allow(missing_docs)]
1391 #[doc(hidden)]
1392 #[inline]
1393 pub fn _bits(&self) -> bool {
1394 match *self {
1395 CTSEW::DISABLED => false,
1396 CTSEW::ENABLED => true,
1397 }
1398 }
1399}
1400#[doc = r" Proxy"]
1401pub struct _CTSEW<'a> {
1402 w: &'a mut W,
1403}
1404impl<'a> _CTSEW<'a> {
1405 #[doc = r" Writes `variant` to the field"]
1406 #[inline]
1407 pub fn variant(self, variant: CTSEW) -> &'a mut W {
1408 {
1409 self.bit(variant._bits())
1410 }
1411 }
1412 #[doc = "CTS hardware flow control disabled"]
1413 #[inline]
1414 pub fn disabled(self) -> &'a mut W {
1415 self.variant(CTSEW::DISABLED)
1416 }
1417 #[doc = "CTS mode enabled, data is only transmitted when the CTS input is asserted"]
1418 #[inline]
1419 pub fn enabled(self) -> &'a mut W {
1420 self.variant(CTSEW::ENABLED)
1421 }
1422 #[doc = r" Sets the field bit"]
1423 pub fn set_bit(self) -> &'a mut W {
1424 self.bit(true)
1425 }
1426 #[doc = r" Clears the field bit"]
1427 pub fn clear_bit(self) -> &'a mut W {
1428 self.bit(false)
1429 }
1430 #[doc = r" Writes raw bits to the field"]
1431 #[inline]
1432 pub fn bit(self, value: bool) -> &'a mut W {
1433 const MASK: bool = true;
1434 const OFFSET: u8 = 9;
1435 self.w.bits &= !((MASK as u32) << OFFSET);
1436 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1437 self.w
1438 }
1439}
1440#[doc = "Values that can be written to the field `RTSE`"]
1441pub enum RTSEW {
1442 #[doc = "RTS hardware flow control disabled"]
1443 DISABLED,
1444 #[doc = "RTS output enabled, data is only requested when there is space in the receive buffer"]
1445 ENABLED,
1446}
1447impl RTSEW {
1448 #[allow(missing_docs)]
1449 #[doc(hidden)]
1450 #[inline]
1451 pub fn _bits(&self) -> bool {
1452 match *self {
1453 RTSEW::DISABLED => false,
1454 RTSEW::ENABLED => true,
1455 }
1456 }
1457}
1458#[doc = r" Proxy"]
1459pub struct _RTSEW<'a> {
1460 w: &'a mut W,
1461}
1462impl<'a> _RTSEW<'a> {
1463 #[doc = r" Writes `variant` to the field"]
1464 #[inline]
1465 pub fn variant(self, variant: RTSEW) -> &'a mut W {
1466 {
1467 self.bit(variant._bits())
1468 }
1469 }
1470 #[doc = "RTS hardware flow control disabled"]
1471 #[inline]
1472 pub fn disabled(self) -> &'a mut W {
1473 self.variant(RTSEW::DISABLED)
1474 }
1475 #[doc = "RTS output enabled, data is only requested when there is space in the receive buffer"]
1476 #[inline]
1477 pub fn enabled(self) -> &'a mut W {
1478 self.variant(RTSEW::ENABLED)
1479 }
1480 #[doc = r" Sets the field bit"]
1481 pub fn set_bit(self) -> &'a mut W {
1482 self.bit(true)
1483 }
1484 #[doc = r" Clears the field bit"]
1485 pub fn clear_bit(self) -> &'a mut W {
1486 self.bit(false)
1487 }
1488 #[doc = r" Writes raw bits to the field"]
1489 #[inline]
1490 pub fn bit(self, value: bool) -> &'a mut W {
1491 const MASK: bool = true;
1492 const OFFSET: u8 = 8;
1493 self.w.bits &= !((MASK as u32) << OFFSET);
1494 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1495 self.w
1496 }
1497}
1498#[doc = "Values that can be written to the field `DMAT`"]
1499pub enum DMATW {
1500 #[doc = "DMA mode is disabled for transmission"]
1501 DISABLED,
1502 #[doc = "DMA mode is enabled for transmission"]
1503 ENABLED,
1504}
1505impl DMATW {
1506 #[allow(missing_docs)]
1507 #[doc(hidden)]
1508 #[inline]
1509 pub fn _bits(&self) -> bool {
1510 match *self {
1511 DMATW::DISABLED => false,
1512 DMATW::ENABLED => true,
1513 }
1514 }
1515}
1516#[doc = r" Proxy"]
1517pub struct _DMATW<'a> {
1518 w: &'a mut W,
1519}
1520impl<'a> _DMATW<'a> {
1521 #[doc = r" Writes `variant` to the field"]
1522 #[inline]
1523 pub fn variant(self, variant: DMATW) -> &'a mut W {
1524 {
1525 self.bit(variant._bits())
1526 }
1527 }
1528 #[doc = "DMA mode is disabled for transmission"]
1529 #[inline]
1530 pub fn disabled(self) -> &'a mut W {
1531 self.variant(DMATW::DISABLED)
1532 }
1533 #[doc = "DMA mode is enabled for transmission"]
1534 #[inline]
1535 pub fn enabled(self) -> &'a mut W {
1536 self.variant(DMATW::ENABLED)
1537 }
1538 #[doc = r" Sets the field bit"]
1539 pub fn set_bit(self) -> &'a mut W {
1540 self.bit(true)
1541 }
1542 #[doc = r" Clears the field bit"]
1543 pub fn clear_bit(self) -> &'a mut W {
1544 self.bit(false)
1545 }
1546 #[doc = r" Writes raw bits to the field"]
1547 #[inline]
1548 pub fn bit(self, value: bool) -> &'a mut W {
1549 const MASK: bool = true;
1550 const OFFSET: u8 = 7;
1551 self.w.bits &= !((MASK as u32) << OFFSET);
1552 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1553 self.w
1554 }
1555}
1556#[doc = "Values that can be written to the field `DMAR`"]
1557pub enum DMARW {
1558 #[doc = "DMA mode is disabled for reception"]
1559 DISABLED,
1560 #[doc = "DMA mode is enabled for reception"]
1561 ENABLED,
1562}
1563impl DMARW {
1564 #[allow(missing_docs)]
1565 #[doc(hidden)]
1566 #[inline]
1567 pub fn _bits(&self) -> bool {
1568 match *self {
1569 DMARW::DISABLED => false,
1570 DMARW::ENABLED => true,
1571 }
1572 }
1573}
1574#[doc = r" Proxy"]
1575pub struct _DMARW<'a> {
1576 w: &'a mut W,
1577}
1578impl<'a> _DMARW<'a> {
1579 #[doc = r" Writes `variant` to the field"]
1580 #[inline]
1581 pub fn variant(self, variant: DMARW) -> &'a mut W {
1582 {
1583 self.bit(variant._bits())
1584 }
1585 }
1586 #[doc = "DMA mode is disabled for reception"]
1587 #[inline]
1588 pub fn disabled(self) -> &'a mut W {
1589 self.variant(DMARW::DISABLED)
1590 }
1591 #[doc = "DMA mode is enabled for reception"]
1592 #[inline]
1593 pub fn enabled(self) -> &'a mut W {
1594 self.variant(DMARW::ENABLED)
1595 }
1596 #[doc = r" Sets the field bit"]
1597 pub fn set_bit(self) -> &'a mut W {
1598 self.bit(true)
1599 }
1600 #[doc = r" Clears the field bit"]
1601 pub fn clear_bit(self) -> &'a mut W {
1602 self.bit(false)
1603 }
1604 #[doc = r" Writes raw bits to the field"]
1605 #[inline]
1606 pub fn bit(self, value: bool) -> &'a mut W {
1607 const MASK: bool = true;
1608 const OFFSET: u8 = 6;
1609 self.w.bits &= !((MASK as u32) << OFFSET);
1610 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1611 self.w
1612 }
1613}
1614#[doc = "Values that can be written to the field `SCEN`"]
1615pub enum SCENW {
1616 #[doc = "Smartcard Mode disabled"]
1617 DISABLED,
1618 #[doc = "Smartcard Mode enabled"]
1619 ENABLED,
1620}
1621impl SCENW {
1622 #[allow(missing_docs)]
1623 #[doc(hidden)]
1624 #[inline]
1625 pub fn _bits(&self) -> bool {
1626 match *self {
1627 SCENW::DISABLED => false,
1628 SCENW::ENABLED => true,
1629 }
1630 }
1631}
1632#[doc = r" Proxy"]
1633pub struct _SCENW<'a> {
1634 w: &'a mut W,
1635}
1636impl<'a> _SCENW<'a> {
1637 #[doc = r" Writes `variant` to the field"]
1638 #[inline]
1639 pub fn variant(self, variant: SCENW) -> &'a mut W {
1640 {
1641 self.bit(variant._bits())
1642 }
1643 }
1644 #[doc = "Smartcard Mode disabled"]
1645 #[inline]
1646 pub fn disabled(self) -> &'a mut W {
1647 self.variant(SCENW::DISABLED)
1648 }
1649 #[doc = "Smartcard Mode enabled"]
1650 #[inline]
1651 pub fn enabled(self) -> &'a mut W {
1652 self.variant(SCENW::ENABLED)
1653 }
1654 #[doc = r" Sets the field bit"]
1655 pub fn set_bit(self) -> &'a mut W {
1656 self.bit(true)
1657 }
1658 #[doc = r" Clears the field bit"]
1659 pub fn clear_bit(self) -> &'a mut W {
1660 self.bit(false)
1661 }
1662 #[doc = r" Writes raw bits to the field"]
1663 #[inline]
1664 pub fn bit(self, value: bool) -> &'a mut W {
1665 const MASK: bool = true;
1666 const OFFSET: u8 = 5;
1667 self.w.bits &= !((MASK as u32) << OFFSET);
1668 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1669 self.w
1670 }
1671}
1672#[doc = "Values that can be written to the field `NACK`"]
1673pub enum NACKW {
1674 #[doc = "NACK transmission in case of parity error is disabled"]
1675 DISABLED,
1676 #[doc = "NACK transmission during parity error is enabled"]
1677 ENABLED,
1678}
1679impl NACKW {
1680 #[allow(missing_docs)]
1681 #[doc(hidden)]
1682 #[inline]
1683 pub fn _bits(&self) -> bool {
1684 match *self {
1685 NACKW::DISABLED => false,
1686 NACKW::ENABLED => true,
1687 }
1688 }
1689}
1690#[doc = r" Proxy"]
1691pub struct _NACKW<'a> {
1692 w: &'a mut W,
1693}
1694impl<'a> _NACKW<'a> {
1695 #[doc = r" Writes `variant` to the field"]
1696 #[inline]
1697 pub fn variant(self, variant: NACKW) -> &'a mut W {
1698 {
1699 self.bit(variant._bits())
1700 }
1701 }
1702 #[doc = "NACK transmission in case of parity error is disabled"]
1703 #[inline]
1704 pub fn disabled(self) -> &'a mut W {
1705 self.variant(NACKW::DISABLED)
1706 }
1707 #[doc = "NACK transmission during parity error is enabled"]
1708 #[inline]
1709 pub fn enabled(self) -> &'a mut W {
1710 self.variant(NACKW::ENABLED)
1711 }
1712 #[doc = r" Sets the field bit"]
1713 pub fn set_bit(self) -> &'a mut W {
1714 self.bit(true)
1715 }
1716 #[doc = r" Clears the field bit"]
1717 pub fn clear_bit(self) -> &'a mut W {
1718 self.bit(false)
1719 }
1720 #[doc = r" Writes raw bits to the field"]
1721 #[inline]
1722 pub fn bit(self, value: bool) -> &'a mut W {
1723 const MASK: bool = true;
1724 const OFFSET: u8 = 4;
1725 self.w.bits &= !((MASK as u32) << OFFSET);
1726 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1727 self.w
1728 }
1729}
1730#[doc = "Values that can be written to the field `HDSEL`"]
1731pub enum HDSELW {
1732 #[doc = "Half duplex mode is not selected"]
1733 NOTSELECTED,
1734 #[doc = "Half duplex mode is selected"]
1735 SELECTED,
1736}
1737impl HDSELW {
1738 #[allow(missing_docs)]
1739 #[doc(hidden)]
1740 #[inline]
1741 pub fn _bits(&self) -> bool {
1742 match *self {
1743 HDSELW::NOTSELECTED => false,
1744 HDSELW::SELECTED => true,
1745 }
1746 }
1747}
1748#[doc = r" Proxy"]
1749pub struct _HDSELW<'a> {
1750 w: &'a mut W,
1751}
1752impl<'a> _HDSELW<'a> {
1753 #[doc = r" Writes `variant` to the field"]
1754 #[inline]
1755 pub fn variant(self, variant: HDSELW) -> &'a mut W {
1756 {
1757 self.bit(variant._bits())
1758 }
1759 }
1760 #[doc = "Half duplex mode is not selected"]
1761 #[inline]
1762 pub fn not_selected(self) -> &'a mut W {
1763 self.variant(HDSELW::NOTSELECTED)
1764 }
1765 #[doc = "Half duplex mode is selected"]
1766 #[inline]
1767 pub fn selected(self) -> &'a mut W {
1768 self.variant(HDSELW::SELECTED)
1769 }
1770 #[doc = r" Sets the field bit"]
1771 pub fn set_bit(self) -> &'a mut W {
1772 self.bit(true)
1773 }
1774 #[doc = r" Clears the field bit"]
1775 pub fn clear_bit(self) -> &'a mut W {
1776 self.bit(false)
1777 }
1778 #[doc = r" Writes raw bits to the field"]
1779 #[inline]
1780 pub fn bit(self, value: bool) -> &'a mut W {
1781 const MASK: bool = true;
1782 const OFFSET: u8 = 3;
1783 self.w.bits &= !((MASK as u32) << OFFSET);
1784 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1785 self.w
1786 }
1787}
1788#[doc = "Values that can be written to the field `IRLP`"]
1789pub enum IRLPW {
1790 #[doc = "Normal mode"]
1791 NORMAL,
1792 #[doc = "Low-power mode"]
1793 LOWPOWER,
1794}
1795impl IRLPW {
1796 #[allow(missing_docs)]
1797 #[doc(hidden)]
1798 #[inline]
1799 pub fn _bits(&self) -> bool {
1800 match *self {
1801 IRLPW::NORMAL => false,
1802 IRLPW::LOWPOWER => true,
1803 }
1804 }
1805}
1806#[doc = r" Proxy"]
1807pub struct _IRLPW<'a> {
1808 w: &'a mut W,
1809}
1810impl<'a> _IRLPW<'a> {
1811 #[doc = r" Writes `variant` to the field"]
1812 #[inline]
1813 pub fn variant(self, variant: IRLPW) -> &'a mut W {
1814 {
1815 self.bit(variant._bits())
1816 }
1817 }
1818 #[doc = "Normal mode"]
1819 #[inline]
1820 pub fn normal(self) -> &'a mut W {
1821 self.variant(IRLPW::NORMAL)
1822 }
1823 #[doc = "Low-power mode"]
1824 #[inline]
1825 pub fn low_power(self) -> &'a mut W {
1826 self.variant(IRLPW::LOWPOWER)
1827 }
1828 #[doc = r" Sets the field bit"]
1829 pub fn set_bit(self) -> &'a mut W {
1830 self.bit(true)
1831 }
1832 #[doc = r" Clears the field bit"]
1833 pub fn clear_bit(self) -> &'a mut W {
1834 self.bit(false)
1835 }
1836 #[doc = r" Writes raw bits to the field"]
1837 #[inline]
1838 pub fn bit(self, value: bool) -> &'a mut W {
1839 const MASK: bool = true;
1840 const OFFSET: u8 = 2;
1841 self.w.bits &= !((MASK as u32) << OFFSET);
1842 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1843 self.w
1844 }
1845}
1846#[doc = "Values that can be written to the field `IREN`"]
1847pub enum IRENW {
1848 #[doc = "IrDA disabled"]
1849 DISABLED,
1850 #[doc = "IrDA enabled"]
1851 ENABLED,
1852}
1853impl IRENW {
1854 #[allow(missing_docs)]
1855 #[doc(hidden)]
1856 #[inline]
1857 pub fn _bits(&self) -> bool {
1858 match *self {
1859 IRENW::DISABLED => false,
1860 IRENW::ENABLED => true,
1861 }
1862 }
1863}
1864#[doc = r" Proxy"]
1865pub struct _IRENW<'a> {
1866 w: &'a mut W,
1867}
1868impl<'a> _IRENW<'a> {
1869 #[doc = r" Writes `variant` to the field"]
1870 #[inline]
1871 pub fn variant(self, variant: IRENW) -> &'a mut W {
1872 {
1873 self.bit(variant._bits())
1874 }
1875 }
1876 #[doc = "IrDA disabled"]
1877 #[inline]
1878 pub fn disabled(self) -> &'a mut W {
1879 self.variant(IRENW::DISABLED)
1880 }
1881 #[doc = "IrDA enabled"]
1882 #[inline]
1883 pub fn enabled(self) -> &'a mut W {
1884 self.variant(IRENW::ENABLED)
1885 }
1886 #[doc = r" Sets the field bit"]
1887 pub fn set_bit(self) -> &'a mut W {
1888 self.bit(true)
1889 }
1890 #[doc = r" Clears the field bit"]
1891 pub fn clear_bit(self) -> &'a mut W {
1892 self.bit(false)
1893 }
1894 #[doc = r" Writes raw bits to the field"]
1895 #[inline]
1896 pub fn bit(self, value: bool) -> &'a mut W {
1897 const MASK: bool = true;
1898 const OFFSET: u8 = 1;
1899 self.w.bits &= !((MASK as u32) << OFFSET);
1900 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1901 self.w
1902 }
1903}
1904#[doc = "Values that can be written to the field `EIE`"]
1905pub enum EIEW {
1906 #[doc = "Interrupt is inhibited"]
1907 DISABLED,
1908 #[doc = "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"]
1909 ENABLED,
1910}
1911impl EIEW {
1912 #[allow(missing_docs)]
1913 #[doc(hidden)]
1914 #[inline]
1915 pub fn _bits(&self) -> bool {
1916 match *self {
1917 EIEW::DISABLED => false,
1918 EIEW::ENABLED => true,
1919 }
1920 }
1921}
1922#[doc = r" Proxy"]
1923pub struct _EIEW<'a> {
1924 w: &'a mut W,
1925}
1926impl<'a> _EIEW<'a> {
1927 #[doc = r" Writes `variant` to the field"]
1928 #[inline]
1929 pub fn variant(self, variant: EIEW) -> &'a mut W {
1930 {
1931 self.bit(variant._bits())
1932 }
1933 }
1934 #[doc = "Interrupt is inhibited"]
1935 #[inline]
1936 pub fn disabled(self) -> &'a mut W {
1937 self.variant(EIEW::DISABLED)
1938 }
1939 #[doc = "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"]
1940 #[inline]
1941 pub fn enabled(self) -> &'a mut W {
1942 self.variant(EIEW::ENABLED)
1943 }
1944 #[doc = r" Sets the field bit"]
1945 pub fn set_bit(self) -> &'a mut W {
1946 self.bit(true)
1947 }
1948 #[doc = r" Clears the field bit"]
1949 pub fn clear_bit(self) -> &'a mut W {
1950 self.bit(false)
1951 }
1952 #[doc = r" Writes raw bits to the field"]
1953 #[inline]
1954 pub fn bit(self, value: bool) -> &'a mut W {
1955 const MASK: bool = true;
1956 const OFFSET: u8 = 0;
1957 self.w.bits &= !((MASK as u32) << OFFSET);
1958 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1959 self.w
1960 }
1961}
1962impl R {
1963 #[doc = r" Value of the register as raw bits"]
1964 #[inline]
1965 pub fn bits(&self) -> u32 {
1966 self.bits
1967 }
1968 #[doc = "Bit 22 - Wakeup from Stop mode interrupt enable"]
1969 #[inline]
1970 pub fn wufie(&self) -> WUFIER {
1971 WUFIER::_from({
1972 const MASK: bool = true;
1973 const OFFSET: u8 = 22;
1974 ((self.bits >> OFFSET) & MASK as u32) != 0
1975 })
1976 }
1977 #[doc = "Bits 20:21 - Wakeup from Stop mode interrupt flag selection"]
1978 #[inline]
1979 pub fn wus(&self) -> WUSR {
1980 WUSR::_from({
1981 const MASK: u8 = 3;
1982 const OFFSET: u8 = 20;
1983 ((self.bits >> OFFSET) & MASK as u32) as u8
1984 })
1985 }
1986 #[doc = "Bits 17:19 - Smartcard auto-retry count"]
1987 #[inline]
1988 pub fn scarcnt(&self) -> SCARCNTR {
1989 let bits = {
1990 const MASK: u8 = 7;
1991 const OFFSET: u8 = 17;
1992 ((self.bits >> OFFSET) & MASK as u32) as u8
1993 };
1994 SCARCNTR { bits }
1995 }
1996 #[doc = "Bit 15 - Driver enable polarity selection"]
1997 #[inline]
1998 pub fn dep(&self) -> DEPR {
1999 DEPR::_from({
2000 const MASK: bool = true;
2001 const OFFSET: u8 = 15;
2002 ((self.bits >> OFFSET) & MASK as u32) != 0
2003 })
2004 }
2005 #[doc = "Bit 14 - Driver enable mode"]
2006 #[inline]
2007 pub fn dem(&self) -> DEMR {
2008 DEMR::_from({
2009 const MASK: bool = true;
2010 const OFFSET: u8 = 14;
2011 ((self.bits >> OFFSET) & MASK as u32) != 0
2012 })
2013 }
2014 #[doc = "Bit 13 - DMA Disable on Reception Error"]
2015 #[inline]
2016 pub fn ddre(&self) -> DDRER {
2017 DDRER::_from({
2018 const MASK: bool = true;
2019 const OFFSET: u8 = 13;
2020 ((self.bits >> OFFSET) & MASK as u32) != 0
2021 })
2022 }
2023 #[doc = "Bit 12 - Overrun Disable"]
2024 #[inline]
2025 pub fn ovrdis(&self) -> OVRDISR {
2026 OVRDISR::_from({
2027 const MASK: bool = true;
2028 const OFFSET: u8 = 12;
2029 ((self.bits >> OFFSET) & MASK as u32) != 0
2030 })
2031 }
2032 #[doc = "Bit 11 - One sample bit method enable"]
2033 #[inline]
2034 pub fn onebit(&self) -> ONEBITR {
2035 ONEBITR::_from({
2036 const MASK: bool = true;
2037 const OFFSET: u8 = 11;
2038 ((self.bits >> OFFSET) & MASK as u32) != 0
2039 })
2040 }
2041 #[doc = "Bit 10 - CTS interrupt enable"]
2042 #[inline]
2043 pub fn ctsie(&self) -> CTSIER {
2044 CTSIER::_from({
2045 const MASK: bool = true;
2046 const OFFSET: u8 = 10;
2047 ((self.bits >> OFFSET) & MASK as u32) != 0
2048 })
2049 }
2050 #[doc = "Bit 9 - CTS enable"]
2051 #[inline]
2052 pub fn ctse(&self) -> CTSER {
2053 CTSER::_from({
2054 const MASK: bool = true;
2055 const OFFSET: u8 = 9;
2056 ((self.bits >> OFFSET) & MASK as u32) != 0
2057 })
2058 }
2059 #[doc = "Bit 8 - RTS enable"]
2060 #[inline]
2061 pub fn rtse(&self) -> RTSER {
2062 RTSER::_from({
2063 const MASK: bool = true;
2064 const OFFSET: u8 = 8;
2065 ((self.bits >> OFFSET) & MASK as u32) != 0
2066 })
2067 }
2068 #[doc = "Bit 7 - DMA enable transmitter"]
2069 #[inline]
2070 pub fn dmat(&self) -> DMATR {
2071 DMATR::_from({
2072 const MASK: bool = true;
2073 const OFFSET: u8 = 7;
2074 ((self.bits >> OFFSET) & MASK as u32) != 0
2075 })
2076 }
2077 #[doc = "Bit 6 - DMA enable receiver"]
2078 #[inline]
2079 pub fn dmar(&self) -> DMARR {
2080 DMARR::_from({
2081 const MASK: bool = true;
2082 const OFFSET: u8 = 6;
2083 ((self.bits >> OFFSET) & MASK as u32) != 0
2084 })
2085 }
2086 #[doc = "Bit 5 - Smartcard mode enable"]
2087 #[inline]
2088 pub fn scen(&self) -> SCENR {
2089 SCENR::_from({
2090 const MASK: bool = true;
2091 const OFFSET: u8 = 5;
2092 ((self.bits >> OFFSET) & MASK as u32) != 0
2093 })
2094 }
2095 #[doc = "Bit 4 - Smartcard NACK enable"]
2096 #[inline]
2097 pub fn nack(&self) -> NACKR {
2098 NACKR::_from({
2099 const MASK: bool = true;
2100 const OFFSET: u8 = 4;
2101 ((self.bits >> OFFSET) & MASK as u32) != 0
2102 })
2103 }
2104 #[doc = "Bit 3 - Half-duplex selection"]
2105 #[inline]
2106 pub fn hdsel(&self) -> HDSELR {
2107 HDSELR::_from({
2108 const MASK: bool = true;
2109 const OFFSET: u8 = 3;
2110 ((self.bits >> OFFSET) & MASK as u32) != 0
2111 })
2112 }
2113 #[doc = "Bit 2 - Ir low-power"]
2114 #[inline]
2115 pub fn irlp(&self) -> IRLPR {
2116 IRLPR::_from({
2117 const MASK: bool = true;
2118 const OFFSET: u8 = 2;
2119 ((self.bits >> OFFSET) & MASK as u32) != 0
2120 })
2121 }
2122 #[doc = "Bit 1 - Ir mode enable"]
2123 #[inline]
2124 pub fn iren(&self) -> IRENR {
2125 IRENR::_from({
2126 const MASK: bool = true;
2127 const OFFSET: u8 = 1;
2128 ((self.bits >> OFFSET) & MASK as u32) != 0
2129 })
2130 }
2131 #[doc = "Bit 0 - Error interrupt enable"]
2132 #[inline]
2133 pub fn eie(&self) -> EIER {
2134 EIER::_from({
2135 const MASK: bool = true;
2136 const OFFSET: u8 = 0;
2137 ((self.bits >> OFFSET) & MASK as u32) != 0
2138 })
2139 }
2140}
2141impl W {
2142 #[doc = r" Reset value of the register"]
2143 #[inline]
2144 pub fn reset_value() -> W {
2145 W { bits: 0 }
2146 }
2147 #[doc = r" Writes raw bits to the register"]
2148 #[inline]
2149 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2150 self.bits = bits;
2151 self
2152 }
2153 #[doc = "Bit 22 - Wakeup from Stop mode interrupt enable"]
2154 #[inline]
2155 pub fn wufie(&mut self) -> _WUFIEW {
2156 _WUFIEW { w: self }
2157 }
2158 #[doc = "Bits 20:21 - Wakeup from Stop mode interrupt flag selection"]
2159 #[inline]
2160 pub fn wus(&mut self) -> _WUSW {
2161 _WUSW { w: self }
2162 }
2163 #[doc = "Bits 17:19 - Smartcard auto-retry count"]
2164 #[inline]
2165 pub fn scarcnt(&mut self) -> _SCARCNTW {
2166 _SCARCNTW { w: self }
2167 }
2168 #[doc = "Bit 15 - Driver enable polarity selection"]
2169 #[inline]
2170 pub fn dep(&mut self) -> _DEPW {
2171 _DEPW { w: self }
2172 }
2173 #[doc = "Bit 14 - Driver enable mode"]
2174 #[inline]
2175 pub fn dem(&mut self) -> _DEMW {
2176 _DEMW { w: self }
2177 }
2178 #[doc = "Bit 13 - DMA Disable on Reception Error"]
2179 #[inline]
2180 pub fn ddre(&mut self) -> _DDREW {
2181 _DDREW { w: self }
2182 }
2183 #[doc = "Bit 12 - Overrun Disable"]
2184 #[inline]
2185 pub fn ovrdis(&mut self) -> _OVRDISW {
2186 _OVRDISW { w: self }
2187 }
2188 #[doc = "Bit 11 - One sample bit method enable"]
2189 #[inline]
2190 pub fn onebit(&mut self) -> _ONEBITW {
2191 _ONEBITW { w: self }
2192 }
2193 #[doc = "Bit 10 - CTS interrupt enable"]
2194 #[inline]
2195 pub fn ctsie(&mut self) -> _CTSIEW {
2196 _CTSIEW { w: self }
2197 }
2198 #[doc = "Bit 9 - CTS enable"]
2199 #[inline]
2200 pub fn ctse(&mut self) -> _CTSEW {
2201 _CTSEW { w: self }
2202 }
2203 #[doc = "Bit 8 - RTS enable"]
2204 #[inline]
2205 pub fn rtse(&mut self) -> _RTSEW {
2206 _RTSEW { w: self }
2207 }
2208 #[doc = "Bit 7 - DMA enable transmitter"]
2209 #[inline]
2210 pub fn dmat(&mut self) -> _DMATW {
2211 _DMATW { w: self }
2212 }
2213 #[doc = "Bit 6 - DMA enable receiver"]
2214 #[inline]
2215 pub fn dmar(&mut self) -> _DMARW {
2216 _DMARW { w: self }
2217 }
2218 #[doc = "Bit 5 - Smartcard mode enable"]
2219 #[inline]
2220 pub fn scen(&mut self) -> _SCENW {
2221 _SCENW { w: self }
2222 }
2223 #[doc = "Bit 4 - Smartcard NACK enable"]
2224 #[inline]
2225 pub fn nack(&mut self) -> _NACKW {
2226 _NACKW { w: self }
2227 }
2228 #[doc = "Bit 3 - Half-duplex selection"]
2229 #[inline]
2230 pub fn hdsel(&mut self) -> _HDSELW {
2231 _HDSELW { w: self }
2232 }
2233 #[doc = "Bit 2 - Ir low-power"]
2234 #[inline]
2235 pub fn irlp(&mut self) -> _IRLPW {
2236 _IRLPW { w: self }
2237 }
2238 #[doc = "Bit 1 - Ir mode enable"]
2239 #[inline]
2240 pub fn iren(&mut self) -> _IRENW {
2241 _IRENW { w: self }
2242 }
2243 #[doc = "Bit 0 - Error interrupt enable"]
2244 #[inline]
2245 pub fn eie(&mut self) -> _EIEW {
2246 _EIEW { w: self }
2247 }
2248}