1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct CTPHR {
47 bits: u8,
48}
49impl CTPHR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = r" Value of the field"]
57pub struct CTPLR {
58 bits: u8,
59}
60impl CTPLR {
61 #[doc = r" Value of the field as raw bits"]
62 #[inline]
63 pub fn bits(&self) -> u8 {
64 self.bits
65 }
66}
67#[doc = r" Value of the field"]
68pub struct SSDR {
69 bits: u8,
70}
71impl SSDR {
72 #[doc = r" Value of the field as raw bits"]
73 #[inline]
74 pub fn bits(&self) -> u8 {
75 self.bits
76 }
77}
78#[doc = r" Value of the field"]
79pub struct SSER {
80 bits: bool,
81}
82impl SSER {
83 #[doc = r" Value of the field as raw bits"]
84 #[inline]
85 pub fn bit(&self) -> bool {
86 self.bits
87 }
88 #[doc = r" Returns `true` if the bit is clear (0)"]
89 #[inline]
90 pub fn bit_is_clear(&self) -> bool {
91 !self.bit()
92 }
93 #[doc = r" Returns `true` if the bit is set (1)"]
94 #[inline]
95 pub fn bit_is_set(&self) -> bool {
96 self.bit()
97 }
98}
99#[doc = r" Value of the field"]
100pub struct SSPSCR {
101 bits: bool,
102}
103impl SSPSCR {
104 #[doc = r" Value of the field as raw bits"]
105 #[inline]
106 pub fn bit(&self) -> bool {
107 self.bits
108 }
109 #[doc = r" Returns `true` if the bit is clear (0)"]
110 #[inline]
111 pub fn bit_is_clear(&self) -> bool {
112 !self.bit()
113 }
114 #[doc = r" Returns `true` if the bit is set (1)"]
115 #[inline]
116 pub fn bit_is_set(&self) -> bool {
117 self.bit()
118 }
119}
120#[doc = r" Value of the field"]
121pub struct PGPSCR {
122 bits: u8,
123}
124impl PGPSCR {
125 #[doc = r" Value of the field as raw bits"]
126 #[inline]
127 pub fn bits(&self) -> u8 {
128 self.bits
129 }
130}
131#[doc = r" Value of the field"]
132pub struct MCVR {
133 bits: u8,
134}
135impl MCVR {
136 #[doc = r" Value of the field as raw bits"]
137 #[inline]
138 pub fn bits(&self) -> u8 {
139 self.bits
140 }
141}
142#[doc = r" Value of the field"]
143pub struct IODEFR {
144 bits: bool,
145}
146impl IODEFR {
147 #[doc = r" Value of the field as raw bits"]
148 #[inline]
149 pub fn bit(&self) -> bool {
150 self.bits
151 }
152 #[doc = r" Returns `true` if the bit is clear (0)"]
153 #[inline]
154 pub fn bit_is_clear(&self) -> bool {
155 !self.bit()
156 }
157 #[doc = r" Returns `true` if the bit is set (1)"]
158 #[inline]
159 pub fn bit_is_set(&self) -> bool {
160 self.bit()
161 }
162}
163#[doc = r" Value of the field"]
164pub struct SYNCPOLR {
165 bits: bool,
166}
167impl SYNCPOLR {
168 #[doc = r" Value of the field as raw bits"]
169 #[inline]
170 pub fn bit(&self) -> bool {
171 self.bits
172 }
173 #[doc = r" Returns `true` if the bit is clear (0)"]
174 #[inline]
175 pub fn bit_is_clear(&self) -> bool {
176 !self.bit()
177 }
178 #[doc = r" Returns `true` if the bit is set (1)"]
179 #[inline]
180 pub fn bit_is_set(&self) -> bool {
181 self.bit()
182 }
183}
184#[doc = r" Value of the field"]
185pub struct AMR {
186 bits: bool,
187}
188impl AMR {
189 #[doc = r" Value of the field as raw bits"]
190 #[inline]
191 pub fn bit(&self) -> bool {
192 self.bits
193 }
194 #[doc = r" Returns `true` if the bit is clear (0)"]
195 #[inline]
196 pub fn bit_is_clear(&self) -> bool {
197 !self.bit()
198 }
199 #[doc = r" Returns `true` if the bit is set (1)"]
200 #[inline]
201 pub fn bit_is_set(&self) -> bool {
202 self.bit()
203 }
204}
205#[doc = r" Value of the field"]
206pub struct STARTR {
207 bits: bool,
208}
209impl STARTR {
210 #[doc = r" Value of the field as raw bits"]
211 #[inline]
212 pub fn bit(&self) -> bool {
213 self.bits
214 }
215 #[doc = r" Returns `true` if the bit is clear (0)"]
216 #[inline]
217 pub fn bit_is_clear(&self) -> bool {
218 !self.bit()
219 }
220 #[doc = r" Returns `true` if the bit is set (1)"]
221 #[inline]
222 pub fn bit_is_set(&self) -> bool {
223 self.bit()
224 }
225}
226#[doc = r" Value of the field"]
227pub struct TSCER {
228 bits: bool,
229}
230impl TSCER {
231 #[doc = r" Value of the field as raw bits"]
232 #[inline]
233 pub fn bit(&self) -> bool {
234 self.bits
235 }
236 #[doc = r" Returns `true` if the bit is clear (0)"]
237 #[inline]
238 pub fn bit_is_clear(&self) -> bool {
239 !self.bit()
240 }
241 #[doc = r" Returns `true` if the bit is set (1)"]
242 #[inline]
243 pub fn bit_is_set(&self) -> bool {
244 self.bit()
245 }
246}
247#[doc = r" Proxy"]
248pub struct _CTPHW<'a> {
249 w: &'a mut W,
250}
251impl<'a> _CTPHW<'a> {
252 #[doc = r" Writes raw bits to the field"]
253 #[inline]
254 pub unsafe fn bits(self, value: u8) -> &'a mut W {
255 const MASK: u8 = 15;
256 const OFFSET: u8 = 28;
257 self.w.bits &= !((MASK as u32) << OFFSET);
258 self.w.bits |= ((value & MASK) as u32) << OFFSET;
259 self.w
260 }
261}
262#[doc = r" Proxy"]
263pub struct _CTPLW<'a> {
264 w: &'a mut W,
265}
266impl<'a> _CTPLW<'a> {
267 #[doc = r" Writes raw bits to the field"]
268 #[inline]
269 pub unsafe fn bits(self, value: u8) -> &'a mut W {
270 const MASK: u8 = 15;
271 const OFFSET: u8 = 24;
272 self.w.bits &= !((MASK as u32) << OFFSET);
273 self.w.bits |= ((value & MASK) as u32) << OFFSET;
274 self.w
275 }
276}
277#[doc = r" Proxy"]
278pub struct _SSDW<'a> {
279 w: &'a mut W,
280}
281impl<'a> _SSDW<'a> {
282 #[doc = r" Writes raw bits to the field"]
283 #[inline]
284 pub unsafe fn bits(self, value: u8) -> &'a mut W {
285 const MASK: u8 = 127;
286 const OFFSET: u8 = 17;
287 self.w.bits &= !((MASK as u32) << OFFSET);
288 self.w.bits |= ((value & MASK) as u32) << OFFSET;
289 self.w
290 }
291}
292#[doc = r" Proxy"]
293pub struct _SSEW<'a> {
294 w: &'a mut W,
295}
296impl<'a> _SSEW<'a> {
297 #[doc = r" Sets the field bit"]
298 pub fn set_bit(self) -> &'a mut W {
299 self.bit(true)
300 }
301 #[doc = r" Clears the field bit"]
302 pub fn clear_bit(self) -> &'a mut W {
303 self.bit(false)
304 }
305 #[doc = r" Writes raw bits to the field"]
306 #[inline]
307 pub fn bit(self, value: bool) -> &'a mut W {
308 const MASK: bool = true;
309 const OFFSET: u8 = 16;
310 self.w.bits &= !((MASK as u32) << OFFSET);
311 self.w.bits |= ((value & MASK) as u32) << OFFSET;
312 self.w
313 }
314}
315#[doc = r" Proxy"]
316pub struct _SSPSCW<'a> {
317 w: &'a mut W,
318}
319impl<'a> _SSPSCW<'a> {
320 #[doc = r" Sets the field bit"]
321 pub fn set_bit(self) -> &'a mut W {
322 self.bit(true)
323 }
324 #[doc = r" Clears the field bit"]
325 pub fn clear_bit(self) -> &'a mut W {
326 self.bit(false)
327 }
328 #[doc = r" Writes raw bits to the field"]
329 #[inline]
330 pub fn bit(self, value: bool) -> &'a mut W {
331 const MASK: bool = true;
332 const OFFSET: u8 = 15;
333 self.w.bits &= !((MASK as u32) << OFFSET);
334 self.w.bits |= ((value & MASK) as u32) << OFFSET;
335 self.w
336 }
337}
338#[doc = r" Proxy"]
339pub struct _PGPSCW<'a> {
340 w: &'a mut W,
341}
342impl<'a> _PGPSCW<'a> {
343 #[doc = r" Writes raw bits to the field"]
344 #[inline]
345 pub unsafe fn bits(self, value: u8) -> &'a mut W {
346 const MASK: u8 = 7;
347 const OFFSET: u8 = 12;
348 self.w.bits &= !((MASK as u32) << OFFSET);
349 self.w.bits |= ((value & MASK) as u32) << OFFSET;
350 self.w
351 }
352}
353#[doc = r" Proxy"]
354pub struct _MCVW<'a> {
355 w: &'a mut W,
356}
357impl<'a> _MCVW<'a> {
358 #[doc = r" Writes raw bits to the field"]
359 #[inline]
360 pub unsafe fn bits(self, value: u8) -> &'a mut W {
361 const MASK: u8 = 7;
362 const OFFSET: u8 = 5;
363 self.w.bits &= !((MASK as u32) << OFFSET);
364 self.w.bits |= ((value & MASK) as u32) << OFFSET;
365 self.w
366 }
367}
368#[doc = r" Proxy"]
369pub struct _IODEFW<'a> {
370 w: &'a mut W,
371}
372impl<'a> _IODEFW<'a> {
373 #[doc = r" Sets the field bit"]
374 pub fn set_bit(self) -> &'a mut W {
375 self.bit(true)
376 }
377 #[doc = r" Clears the field bit"]
378 pub fn clear_bit(self) -> &'a mut W {
379 self.bit(false)
380 }
381 #[doc = r" Writes raw bits to the field"]
382 #[inline]
383 pub fn bit(self, value: bool) -> &'a mut W {
384 const MASK: bool = true;
385 const OFFSET: u8 = 4;
386 self.w.bits &= !((MASK as u32) << OFFSET);
387 self.w.bits |= ((value & MASK) as u32) << OFFSET;
388 self.w
389 }
390}
391#[doc = r" Proxy"]
392pub struct _SYNCPOLW<'a> {
393 w: &'a mut W,
394}
395impl<'a> _SYNCPOLW<'a> {
396 #[doc = r" Sets the field bit"]
397 pub fn set_bit(self) -> &'a mut W {
398 self.bit(true)
399 }
400 #[doc = r" Clears the field bit"]
401 pub fn clear_bit(self) -> &'a mut W {
402 self.bit(false)
403 }
404 #[doc = r" Writes raw bits to the field"]
405 #[inline]
406 pub fn bit(self, value: bool) -> &'a mut W {
407 const MASK: bool = true;
408 const OFFSET: u8 = 3;
409 self.w.bits &= !((MASK as u32) << OFFSET);
410 self.w.bits |= ((value & MASK) as u32) << OFFSET;
411 self.w
412 }
413}
414#[doc = r" Proxy"]
415pub struct _AMW<'a> {
416 w: &'a mut W,
417}
418impl<'a> _AMW<'a> {
419 #[doc = r" Sets the field bit"]
420 pub fn set_bit(self) -> &'a mut W {
421 self.bit(true)
422 }
423 #[doc = r" Clears the field bit"]
424 pub fn clear_bit(self) -> &'a mut W {
425 self.bit(false)
426 }
427 #[doc = r" Writes raw bits to the field"]
428 #[inline]
429 pub fn bit(self, value: bool) -> &'a mut W {
430 const MASK: bool = true;
431 const OFFSET: u8 = 2;
432 self.w.bits &= !((MASK as u32) << OFFSET);
433 self.w.bits |= ((value & MASK) as u32) << OFFSET;
434 self.w
435 }
436}
437#[doc = r" Proxy"]
438pub struct _STARTW<'a> {
439 w: &'a mut W,
440}
441impl<'a> _STARTW<'a> {
442 #[doc = r" Sets the field bit"]
443 pub fn set_bit(self) -> &'a mut W {
444 self.bit(true)
445 }
446 #[doc = r" Clears the field bit"]
447 pub fn clear_bit(self) -> &'a mut W {
448 self.bit(false)
449 }
450 #[doc = r" Writes raw bits to the field"]
451 #[inline]
452 pub fn bit(self, value: bool) -> &'a mut W {
453 const MASK: bool = true;
454 const OFFSET: u8 = 1;
455 self.w.bits &= !((MASK as u32) << OFFSET);
456 self.w.bits |= ((value & MASK) as u32) << OFFSET;
457 self.w
458 }
459}
460#[doc = r" Proxy"]
461pub struct _TSCEW<'a> {
462 w: &'a mut W,
463}
464impl<'a> _TSCEW<'a> {
465 #[doc = r" Sets the field bit"]
466 pub fn set_bit(self) -> &'a mut W {
467 self.bit(true)
468 }
469 #[doc = r" Clears the field bit"]
470 pub fn clear_bit(self) -> &'a mut W {
471 self.bit(false)
472 }
473 #[doc = r" Writes raw bits to the field"]
474 #[inline]
475 pub fn bit(self, value: bool) -> &'a mut W {
476 const MASK: bool = true;
477 const OFFSET: u8 = 0;
478 self.w.bits &= !((MASK as u32) << OFFSET);
479 self.w.bits |= ((value & MASK) as u32) << OFFSET;
480 self.w
481 }
482}
483impl R {
484 #[doc = r" Value of the register as raw bits"]
485 #[inline]
486 pub fn bits(&self) -> u32 {
487 self.bits
488 }
489 #[doc = "Bits 28:31 - Charge transfer pulse high"]
490 #[inline]
491 pub fn ctph(&self) -> CTPHR {
492 let bits = {
493 const MASK: u8 = 15;
494 const OFFSET: u8 = 28;
495 ((self.bits >> OFFSET) & MASK as u32) as u8
496 };
497 CTPHR { bits }
498 }
499 #[doc = "Bits 24:27 - Charge transfer pulse low"]
500 #[inline]
501 pub fn ctpl(&self) -> CTPLR {
502 let bits = {
503 const MASK: u8 = 15;
504 const OFFSET: u8 = 24;
505 ((self.bits >> OFFSET) & MASK as u32) as u8
506 };
507 CTPLR { bits }
508 }
509 #[doc = "Bits 17:23 - Spread spectrum deviation"]
510 #[inline]
511 pub fn ssd(&self) -> SSDR {
512 let bits = {
513 const MASK: u8 = 127;
514 const OFFSET: u8 = 17;
515 ((self.bits >> OFFSET) & MASK as u32) as u8
516 };
517 SSDR { bits }
518 }
519 #[doc = "Bit 16 - Spread spectrum enable"]
520 #[inline]
521 pub fn sse(&self) -> SSER {
522 let bits = {
523 const MASK: bool = true;
524 const OFFSET: u8 = 16;
525 ((self.bits >> OFFSET) & MASK as u32) != 0
526 };
527 SSER { bits }
528 }
529 #[doc = "Bit 15 - Spread spectrum prescaler"]
530 #[inline]
531 pub fn sspsc(&self) -> SSPSCR {
532 let bits = {
533 const MASK: bool = true;
534 const OFFSET: u8 = 15;
535 ((self.bits >> OFFSET) & MASK as u32) != 0
536 };
537 SSPSCR { bits }
538 }
539 #[doc = "Bits 12:14 - pulse generator prescaler"]
540 #[inline]
541 pub fn pgpsc(&self) -> PGPSCR {
542 let bits = {
543 const MASK: u8 = 7;
544 const OFFSET: u8 = 12;
545 ((self.bits >> OFFSET) & MASK as u32) as u8
546 };
547 PGPSCR { bits }
548 }
549 #[doc = "Bits 5:7 - Max count value"]
550 #[inline]
551 pub fn mcv(&self) -> MCVR {
552 let bits = {
553 const MASK: u8 = 7;
554 const OFFSET: u8 = 5;
555 ((self.bits >> OFFSET) & MASK as u32) as u8
556 };
557 MCVR { bits }
558 }
559 #[doc = "Bit 4 - I/O Default mode"]
560 #[inline]
561 pub fn iodef(&self) -> IODEFR {
562 let bits = {
563 const MASK: bool = true;
564 const OFFSET: u8 = 4;
565 ((self.bits >> OFFSET) & MASK as u32) != 0
566 };
567 IODEFR { bits }
568 }
569 #[doc = "Bit 3 - Synchronization pin polarity"]
570 #[inline]
571 pub fn syncpol(&self) -> SYNCPOLR {
572 let bits = {
573 const MASK: bool = true;
574 const OFFSET: u8 = 3;
575 ((self.bits >> OFFSET) & MASK as u32) != 0
576 };
577 SYNCPOLR { bits }
578 }
579 #[doc = "Bit 2 - Acquisition mode"]
580 #[inline]
581 pub fn am(&self) -> AMR {
582 let bits = {
583 const MASK: bool = true;
584 const OFFSET: u8 = 2;
585 ((self.bits >> OFFSET) & MASK as u32) != 0
586 };
587 AMR { bits }
588 }
589 #[doc = "Bit 1 - Start a new acquisition"]
590 #[inline]
591 pub fn start(&self) -> STARTR {
592 let bits = {
593 const MASK: bool = true;
594 const OFFSET: u8 = 1;
595 ((self.bits >> OFFSET) & MASK as u32) != 0
596 };
597 STARTR { bits }
598 }
599 #[doc = "Bit 0 - Touch sensing controller enable"]
600 #[inline]
601 pub fn tsce(&self) -> TSCER {
602 let bits = {
603 const MASK: bool = true;
604 const OFFSET: u8 = 0;
605 ((self.bits >> OFFSET) & MASK as u32) != 0
606 };
607 TSCER { bits }
608 }
609}
610impl W {
611 #[doc = r" Reset value of the register"]
612 #[inline]
613 pub fn reset_value() -> W {
614 W { bits: 0 }
615 }
616 #[doc = r" Writes raw bits to the register"]
617 #[inline]
618 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
619 self.bits = bits;
620 self
621 }
622 #[doc = "Bits 28:31 - Charge transfer pulse high"]
623 #[inline]
624 pub fn ctph(&mut self) -> _CTPHW {
625 _CTPHW { w: self }
626 }
627 #[doc = "Bits 24:27 - Charge transfer pulse low"]
628 #[inline]
629 pub fn ctpl(&mut self) -> _CTPLW {
630 _CTPLW { w: self }
631 }
632 #[doc = "Bits 17:23 - Spread spectrum deviation"]
633 #[inline]
634 pub fn ssd(&mut self) -> _SSDW {
635 _SSDW { w: self }
636 }
637 #[doc = "Bit 16 - Spread spectrum enable"]
638 #[inline]
639 pub fn sse(&mut self) -> _SSEW {
640 _SSEW { w: self }
641 }
642 #[doc = "Bit 15 - Spread spectrum prescaler"]
643 #[inline]
644 pub fn sspsc(&mut self) -> _SSPSCW {
645 _SSPSCW { w: self }
646 }
647 #[doc = "Bits 12:14 - pulse generator prescaler"]
648 #[inline]
649 pub fn pgpsc(&mut self) -> _PGPSCW {
650 _PGPSCW { w: self }
651 }
652 #[doc = "Bits 5:7 - Max count value"]
653 #[inline]
654 pub fn mcv(&mut self) -> _MCVW {
655 _MCVW { w: self }
656 }
657 #[doc = "Bit 4 - I/O Default mode"]
658 #[inline]
659 pub fn iodef(&mut self) -> _IODEFW {
660 _IODEFW { w: self }
661 }
662 #[doc = "Bit 3 - Synchronization pin polarity"]
663 #[inline]
664 pub fn syncpol(&mut self) -> _SYNCPOLW {
665 _SYNCPOLW { w: self }
666 }
667 #[doc = "Bit 2 - Acquisition mode"]
668 #[inline]
669 pub fn am(&mut self) -> _AMW {
670 _AMW { w: self }
671 }
672 #[doc = "Bit 1 - Start a new acquisition"]
673 #[inline]
674 pub fn start(&mut self) -> _STARTW {
675 _STARTW { w: self }
676 }
677 #[doc = "Bit 0 - Touch sensing controller enable"]
678 #[inline]
679 pub fn tsce(&mut self) -> _TSCEW {
680 _TSCEW { w: self }
681 }
682}