stm32l4x2_pac/sdmmc/
clkcr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CLKCR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct HWFC_ENR {
47    bits: bool,
48}
49impl HWFC_ENR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct NEGEDGER {
68    bits: bool,
69}
70impl NEGEDGER {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct WIDBUSR {
89    bits: u8,
90}
91impl WIDBUSR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bits(&self) -> u8 {
95        self.bits
96    }
97}
98#[doc = r" Value of the field"]
99pub struct BYPASSR {
100    bits: bool,
101}
102impl BYPASSR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bit(&self) -> bool {
106        self.bits
107    }
108    #[doc = r" Returns `true` if the bit is clear (0)"]
109    #[inline]
110    pub fn bit_is_clear(&self) -> bool {
111        !self.bit()
112    }
113    #[doc = r" Returns `true` if the bit is set (1)"]
114    #[inline]
115    pub fn bit_is_set(&self) -> bool {
116        self.bit()
117    }
118}
119#[doc = r" Value of the field"]
120pub struct PWRSAVR {
121    bits: bool,
122}
123impl PWRSAVR {
124    #[doc = r" Value of the field as raw bits"]
125    #[inline]
126    pub fn bit(&self) -> bool {
127        self.bits
128    }
129    #[doc = r" Returns `true` if the bit is clear (0)"]
130    #[inline]
131    pub fn bit_is_clear(&self) -> bool {
132        !self.bit()
133    }
134    #[doc = r" Returns `true` if the bit is set (1)"]
135    #[inline]
136    pub fn bit_is_set(&self) -> bool {
137        self.bit()
138    }
139}
140#[doc = r" Value of the field"]
141pub struct CLKENR {
142    bits: bool,
143}
144impl CLKENR {
145    #[doc = r" Value of the field as raw bits"]
146    #[inline]
147    pub fn bit(&self) -> bool {
148        self.bits
149    }
150    #[doc = r" Returns `true` if the bit is clear (0)"]
151    #[inline]
152    pub fn bit_is_clear(&self) -> bool {
153        !self.bit()
154    }
155    #[doc = r" Returns `true` if the bit is set (1)"]
156    #[inline]
157    pub fn bit_is_set(&self) -> bool {
158        self.bit()
159    }
160}
161#[doc = r" Value of the field"]
162pub struct CLKDIVR {
163    bits: u8,
164}
165impl CLKDIVR {
166    #[doc = r" Value of the field as raw bits"]
167    #[inline]
168    pub fn bits(&self) -> u8 {
169        self.bits
170    }
171}
172#[doc = r" Proxy"]
173pub struct _HWFC_ENW<'a> {
174    w: &'a mut W,
175}
176impl<'a> _HWFC_ENW<'a> {
177    #[doc = r" Sets the field bit"]
178    pub fn set_bit(self) -> &'a mut W {
179        self.bit(true)
180    }
181    #[doc = r" Clears the field bit"]
182    pub fn clear_bit(self) -> &'a mut W {
183        self.bit(false)
184    }
185    #[doc = r" Writes raw bits to the field"]
186    #[inline]
187    pub fn bit(self, value: bool) -> &'a mut W {
188        const MASK: bool = true;
189        const OFFSET: u8 = 14;
190        self.w.bits &= !((MASK as u32) << OFFSET);
191        self.w.bits |= ((value & MASK) as u32) << OFFSET;
192        self.w
193    }
194}
195#[doc = r" Proxy"]
196pub struct _NEGEDGEW<'a> {
197    w: &'a mut W,
198}
199impl<'a> _NEGEDGEW<'a> {
200    #[doc = r" Sets the field bit"]
201    pub fn set_bit(self) -> &'a mut W {
202        self.bit(true)
203    }
204    #[doc = r" Clears the field bit"]
205    pub fn clear_bit(self) -> &'a mut W {
206        self.bit(false)
207    }
208    #[doc = r" Writes raw bits to the field"]
209    #[inline]
210    pub fn bit(self, value: bool) -> &'a mut W {
211        const MASK: bool = true;
212        const OFFSET: u8 = 13;
213        self.w.bits &= !((MASK as u32) << OFFSET);
214        self.w.bits |= ((value & MASK) as u32) << OFFSET;
215        self.w
216    }
217}
218#[doc = r" Proxy"]
219pub struct _WIDBUSW<'a> {
220    w: &'a mut W,
221}
222impl<'a> _WIDBUSW<'a> {
223    #[doc = r" Writes raw bits to the field"]
224    #[inline]
225    pub unsafe fn bits(self, value: u8) -> &'a mut W {
226        const MASK: u8 = 3;
227        const OFFSET: u8 = 11;
228        self.w.bits &= !((MASK as u32) << OFFSET);
229        self.w.bits |= ((value & MASK) as u32) << OFFSET;
230        self.w
231    }
232}
233#[doc = r" Proxy"]
234pub struct _BYPASSW<'a> {
235    w: &'a mut W,
236}
237impl<'a> _BYPASSW<'a> {
238    #[doc = r" Sets the field bit"]
239    pub fn set_bit(self) -> &'a mut W {
240        self.bit(true)
241    }
242    #[doc = r" Clears the field bit"]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r" Writes raw bits to the field"]
247    #[inline]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        const MASK: bool = true;
250        const OFFSET: u8 = 10;
251        self.w.bits &= !((MASK as u32) << OFFSET);
252        self.w.bits |= ((value & MASK) as u32) << OFFSET;
253        self.w
254    }
255}
256#[doc = r" Proxy"]
257pub struct _PWRSAVW<'a> {
258    w: &'a mut W,
259}
260impl<'a> _PWRSAVW<'a> {
261    #[doc = r" Sets the field bit"]
262    pub fn set_bit(self) -> &'a mut W {
263        self.bit(true)
264    }
265    #[doc = r" Clears the field bit"]
266    pub fn clear_bit(self) -> &'a mut W {
267        self.bit(false)
268    }
269    #[doc = r" Writes raw bits to the field"]
270    #[inline]
271    pub fn bit(self, value: bool) -> &'a mut W {
272        const MASK: bool = true;
273        const OFFSET: u8 = 9;
274        self.w.bits &= !((MASK as u32) << OFFSET);
275        self.w.bits |= ((value & MASK) as u32) << OFFSET;
276        self.w
277    }
278}
279#[doc = r" Proxy"]
280pub struct _CLKENW<'a> {
281    w: &'a mut W,
282}
283impl<'a> _CLKENW<'a> {
284    #[doc = r" Sets the field bit"]
285    pub fn set_bit(self) -> &'a mut W {
286        self.bit(true)
287    }
288    #[doc = r" Clears the field bit"]
289    pub fn clear_bit(self) -> &'a mut W {
290        self.bit(false)
291    }
292    #[doc = r" Writes raw bits to the field"]
293    #[inline]
294    pub fn bit(self, value: bool) -> &'a mut W {
295        const MASK: bool = true;
296        const OFFSET: u8 = 8;
297        self.w.bits &= !((MASK as u32) << OFFSET);
298        self.w.bits |= ((value & MASK) as u32) << OFFSET;
299        self.w
300    }
301}
302#[doc = r" Proxy"]
303pub struct _CLKDIVW<'a> {
304    w: &'a mut W,
305}
306impl<'a> _CLKDIVW<'a> {
307    #[doc = r" Writes raw bits to the field"]
308    #[inline]
309    pub unsafe fn bits(self, value: u8) -> &'a mut W {
310        const MASK: u8 = 255;
311        const OFFSET: u8 = 0;
312        self.w.bits &= !((MASK as u32) << OFFSET);
313        self.w.bits |= ((value & MASK) as u32) << OFFSET;
314        self.w
315    }
316}
317impl R {
318    #[doc = r" Value of the register as raw bits"]
319    #[inline]
320    pub fn bits(&self) -> u32 {
321        self.bits
322    }
323    #[doc = "Bit 14 - HW Flow Control enable"]
324    #[inline]
325    pub fn hwfc_en(&self) -> HWFC_ENR {
326        let bits = {
327            const MASK: bool = true;
328            const OFFSET: u8 = 14;
329            ((self.bits >> OFFSET) & MASK as u32) != 0
330        };
331        HWFC_ENR { bits }
332    }
333    #[doc = "Bit 13 - SDIO_CK dephasing selection bit"]
334    #[inline]
335    pub fn negedge(&self) -> NEGEDGER {
336        let bits = {
337            const MASK: bool = true;
338            const OFFSET: u8 = 13;
339            ((self.bits >> OFFSET) & MASK as u32) != 0
340        };
341        NEGEDGER { bits }
342    }
343    #[doc = "Bits 11:12 - Wide bus mode enable bit"]
344    #[inline]
345    pub fn widbus(&self) -> WIDBUSR {
346        let bits = {
347            const MASK: u8 = 3;
348            const OFFSET: u8 = 11;
349            ((self.bits >> OFFSET) & MASK as u32) as u8
350        };
351        WIDBUSR { bits }
352    }
353    #[doc = "Bit 10 - Clock divider bypass enable bit"]
354    #[inline]
355    pub fn bypass(&self) -> BYPASSR {
356        let bits = {
357            const MASK: bool = true;
358            const OFFSET: u8 = 10;
359            ((self.bits >> OFFSET) & MASK as u32) != 0
360        };
361        BYPASSR { bits }
362    }
363    #[doc = "Bit 9 - Power saving configuration bit"]
364    #[inline]
365    pub fn pwrsav(&self) -> PWRSAVR {
366        let bits = {
367            const MASK: bool = true;
368            const OFFSET: u8 = 9;
369            ((self.bits >> OFFSET) & MASK as u32) != 0
370        };
371        PWRSAVR { bits }
372    }
373    #[doc = "Bit 8 - Clock enable bit"]
374    #[inline]
375    pub fn clken(&self) -> CLKENR {
376        let bits = {
377            const MASK: bool = true;
378            const OFFSET: u8 = 8;
379            ((self.bits >> OFFSET) & MASK as u32) != 0
380        };
381        CLKENR { bits }
382    }
383    #[doc = "Bits 0:7 - Clock divide factor"]
384    #[inline]
385    pub fn clkdiv(&self) -> CLKDIVR {
386        let bits = {
387            const MASK: u8 = 255;
388            const OFFSET: u8 = 0;
389            ((self.bits >> OFFSET) & MASK as u32) as u8
390        };
391        CLKDIVR { bits }
392    }
393}
394impl W {
395    #[doc = r" Reset value of the register"]
396    #[inline]
397    pub fn reset_value() -> W {
398        W { bits: 0 }
399    }
400    #[doc = r" Writes raw bits to the register"]
401    #[inline]
402    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
403        self.bits = bits;
404        self
405    }
406    #[doc = "Bit 14 - HW Flow Control enable"]
407    #[inline]
408    pub fn hwfc_en(&mut self) -> _HWFC_ENW {
409        _HWFC_ENW { w: self }
410    }
411    #[doc = "Bit 13 - SDIO_CK dephasing selection bit"]
412    #[inline]
413    pub fn negedge(&mut self) -> _NEGEDGEW {
414        _NEGEDGEW { w: self }
415    }
416    #[doc = "Bits 11:12 - Wide bus mode enable bit"]
417    #[inline]
418    pub fn widbus(&mut self) -> _WIDBUSW {
419        _WIDBUSW { w: self }
420    }
421    #[doc = "Bit 10 - Clock divider bypass enable bit"]
422    #[inline]
423    pub fn bypass(&mut self) -> _BYPASSW {
424        _BYPASSW { w: self }
425    }
426    #[doc = "Bit 9 - Power saving configuration bit"]
427    #[inline]
428    pub fn pwrsav(&mut self) -> _PWRSAVW {
429        _PWRSAVW { w: self }
430    }
431    #[doc = "Bit 8 - Clock enable bit"]
432    #[inline]
433    pub fn clken(&mut self) -> _CLKENW {
434        _CLKENW { w: self }
435    }
436    #[doc = "Bits 0:7 - Clock divide factor"]
437    #[inline]
438    pub fn clkdiv(&mut self) -> _CLKDIVW {
439        _CLKDIVW { w: self }
440    }
441}
stm32l4x2_pac/sdmmc/clkcr.rs

stm32l4x2_pac/sdmmc/
clkcr.rs
