stm32l4x2_pac/rcc/
pllsai1cfgr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::PLLSAI1CFGR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct PLLSAI1RR {
47    bits: u8,
48}
49impl PLLSAI1RR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct PLLSAI1RENR {
58    bits: bool,
59}
60impl PLLSAI1RENR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct PLLSAI1QR {
79    bits: u8,
80}
81impl PLLSAI1QR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bits(&self) -> u8 {
85        self.bits
86    }
87}
88#[doc = r" Value of the field"]
89pub struct PLLSAI1QENR {
90    bits: bool,
91}
92impl PLLSAI1QENR {
93    #[doc = r" Value of the field as raw bits"]
94    #[inline]
95    pub fn bit(&self) -> bool {
96        self.bits
97    }
98    #[doc = r" Returns `true` if the bit is clear (0)"]
99    #[inline]
100    pub fn bit_is_clear(&self) -> bool {
101        !self.bit()
102    }
103    #[doc = r" Returns `true` if the bit is set (1)"]
104    #[inline]
105    pub fn bit_is_set(&self) -> bool {
106        self.bit()
107    }
108}
109#[doc = r" Value of the field"]
110pub struct PLLSAI1PR {
111    bits: bool,
112}
113impl PLLSAI1PR {
114    #[doc = r" Value of the field as raw bits"]
115    #[inline]
116    pub fn bit(&self) -> bool {
117        self.bits
118    }
119    #[doc = r" Returns `true` if the bit is clear (0)"]
120    #[inline]
121    pub fn bit_is_clear(&self) -> bool {
122        !self.bit()
123    }
124    #[doc = r" Returns `true` if the bit is set (1)"]
125    #[inline]
126    pub fn bit_is_set(&self) -> bool {
127        self.bit()
128    }
129}
130#[doc = r" Value of the field"]
131pub struct PLLSAI1PENR {
132    bits: bool,
133}
134impl PLLSAI1PENR {
135    #[doc = r" Value of the field as raw bits"]
136    #[inline]
137    pub fn bit(&self) -> bool {
138        self.bits
139    }
140    #[doc = r" Returns `true` if the bit is clear (0)"]
141    #[inline]
142    pub fn bit_is_clear(&self) -> bool {
143        !self.bit()
144    }
145    #[doc = r" Returns `true` if the bit is set (1)"]
146    #[inline]
147    pub fn bit_is_set(&self) -> bool {
148        self.bit()
149    }
150}
151#[doc = r" Value of the field"]
152pub struct PLLSAI1NR {
153    bits: u8,
154}
155impl PLLSAI1NR {
156    #[doc = r" Value of the field as raw bits"]
157    #[inline]
158    pub fn bits(&self) -> u8 {
159        self.bits
160    }
161}
162#[doc = r" Value of the field"]
163pub struct PLLSAI1PDIVR {
164    bits: u8,
165}
166impl PLLSAI1PDIVR {
167    #[doc = r" Value of the field as raw bits"]
168    #[inline]
169    pub fn bits(&self) -> u8 {
170        self.bits
171    }
172}
173#[doc = r" Proxy"]
174pub struct _PLLSAI1RW<'a> {
175    w: &'a mut W,
176}
177impl<'a> _PLLSAI1RW<'a> {
178    #[doc = r" Writes raw bits to the field"]
179    #[inline]
180    pub unsafe fn bits(self, value: u8) -> &'a mut W {
181        const MASK: u8 = 3;
182        const OFFSET: u8 = 25;
183        self.w.bits &= !((MASK as u32) << OFFSET);
184        self.w.bits |= ((value & MASK) as u32) << OFFSET;
185        self.w
186    }
187}
188#[doc = r" Proxy"]
189pub struct _PLLSAI1RENW<'a> {
190    w: &'a mut W,
191}
192impl<'a> _PLLSAI1RENW<'a> {
193    #[doc = r" Sets the field bit"]
194    pub fn set_bit(self) -> &'a mut W {
195        self.bit(true)
196    }
197    #[doc = r" Clears the field bit"]
198    pub fn clear_bit(self) -> &'a mut W {
199        self.bit(false)
200    }
201    #[doc = r" Writes raw bits to the field"]
202    #[inline]
203    pub fn bit(self, value: bool) -> &'a mut W {
204        const MASK: bool = true;
205        const OFFSET: u8 = 24;
206        self.w.bits &= !((MASK as u32) << OFFSET);
207        self.w.bits |= ((value & MASK) as u32) << OFFSET;
208        self.w
209    }
210}
211#[doc = r" Proxy"]
212pub struct _PLLSAI1QW<'a> {
213    w: &'a mut W,
214}
215impl<'a> _PLLSAI1QW<'a> {
216    #[doc = r" Writes raw bits to the field"]
217    #[inline]
218    pub unsafe fn bits(self, value: u8) -> &'a mut W {
219        const MASK: u8 = 3;
220        const OFFSET: u8 = 21;
221        self.w.bits &= !((MASK as u32) << OFFSET);
222        self.w.bits |= ((value & MASK) as u32) << OFFSET;
223        self.w
224    }
225}
226#[doc = r" Proxy"]
227pub struct _PLLSAI1QENW<'a> {
228    w: &'a mut W,
229}
230impl<'a> _PLLSAI1QENW<'a> {
231    #[doc = r" Sets the field bit"]
232    pub fn set_bit(self) -> &'a mut W {
233        self.bit(true)
234    }
235    #[doc = r" Clears the field bit"]
236    pub fn clear_bit(self) -> &'a mut W {
237        self.bit(false)
238    }
239    #[doc = r" Writes raw bits to the field"]
240    #[inline]
241    pub fn bit(self, value: bool) -> &'a mut W {
242        const MASK: bool = true;
243        const OFFSET: u8 = 20;
244        self.w.bits &= !((MASK as u32) << OFFSET);
245        self.w.bits |= ((value & MASK) as u32) << OFFSET;
246        self.w
247    }
248}
249#[doc = r" Proxy"]
250pub struct _PLLSAI1PW<'a> {
251    w: &'a mut W,
252}
253impl<'a> _PLLSAI1PW<'a> {
254    #[doc = r" Sets the field bit"]
255    pub fn set_bit(self) -> &'a mut W {
256        self.bit(true)
257    }
258    #[doc = r" Clears the field bit"]
259    pub fn clear_bit(self) -> &'a mut W {
260        self.bit(false)
261    }
262    #[doc = r" Writes raw bits to the field"]
263    #[inline]
264    pub fn bit(self, value: bool) -> &'a mut W {
265        const MASK: bool = true;
266        const OFFSET: u8 = 17;
267        self.w.bits &= !((MASK as u32) << OFFSET);
268        self.w.bits |= ((value & MASK) as u32) << OFFSET;
269        self.w
270    }
271}
272#[doc = r" Proxy"]
273pub struct _PLLSAI1PENW<'a> {
274    w: &'a mut W,
275}
276impl<'a> _PLLSAI1PENW<'a> {
277    #[doc = r" Sets the field bit"]
278    pub fn set_bit(self) -> &'a mut W {
279        self.bit(true)
280    }
281    #[doc = r" Clears the field bit"]
282    pub fn clear_bit(self) -> &'a mut W {
283        self.bit(false)
284    }
285    #[doc = r" Writes raw bits to the field"]
286    #[inline]
287    pub fn bit(self, value: bool) -> &'a mut W {
288        const MASK: bool = true;
289        const OFFSET: u8 = 16;
290        self.w.bits &= !((MASK as u32) << OFFSET);
291        self.w.bits |= ((value & MASK) as u32) << OFFSET;
292        self.w
293    }
294}
295#[doc = r" Proxy"]
296pub struct _PLLSAI1NW<'a> {
297    w: &'a mut W,
298}
299impl<'a> _PLLSAI1NW<'a> {
300    #[doc = r" Writes raw bits to the field"]
301    #[inline]
302    pub unsafe fn bits(self, value: u8) -> &'a mut W {
303        const MASK: u8 = 127;
304        const OFFSET: u8 = 8;
305        self.w.bits &= !((MASK as u32) << OFFSET);
306        self.w.bits |= ((value & MASK) as u32) << OFFSET;
307        self.w
308    }
309}
310#[doc = r" Proxy"]
311pub struct _PLLSAI1PDIVW<'a> {
312    w: &'a mut W,
313}
314impl<'a> _PLLSAI1PDIVW<'a> {
315    #[doc = r" Writes raw bits to the field"]
316    #[inline]
317    pub unsafe fn bits(self, value: u8) -> &'a mut W {
318        const MASK: u8 = 31;
319        const OFFSET: u8 = 27;
320        self.w.bits &= !((MASK as u32) << OFFSET);
321        self.w.bits |= ((value & MASK) as u32) << OFFSET;
322        self.w
323    }
324}
325impl R {
326    #[doc = r" Value of the register as raw bits"]
327    #[inline]
328    pub fn bits(&self) -> u32 {
329        self.bits
330    }
331    #[doc = "Bits 25:26 - PLLSAI1 division factor for PLLADC1CLK (ADC clock)"]
332    #[inline]
333    pub fn pllsai1r(&self) -> PLLSAI1RR {
334        let bits = {
335            const MASK: u8 = 3;
336            const OFFSET: u8 = 25;
337            ((self.bits >> OFFSET) & MASK as u32) as u8
338        };
339        PLLSAI1RR { bits }
340    }
341    #[doc = "Bit 24 - PLLSAI1 PLLADC1CLK output enable"]
342    #[inline]
343    pub fn pllsai1ren(&self) -> PLLSAI1RENR {
344        let bits = {
345            const MASK: bool = true;
346            const OFFSET: u8 = 24;
347            ((self.bits >> OFFSET) & MASK as u32) != 0
348        };
349        PLLSAI1RENR { bits }
350    }
351    #[doc = "Bits 21:22 - SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)"]
352    #[inline]
353    pub fn pllsai1q(&self) -> PLLSAI1QR {
354        let bits = {
355            const MASK: u8 = 3;
356            const OFFSET: u8 = 21;
357            ((self.bits >> OFFSET) & MASK as u32) as u8
358        };
359        PLLSAI1QR { bits }
360    }
361    #[doc = "Bit 20 - SAI1PLL PLLUSB2CLK output enable"]
362    #[inline]
363    pub fn pllsai1qen(&self) -> PLLSAI1QENR {
364        let bits = {
365            const MASK: bool = true;
366            const OFFSET: u8 = 20;
367            ((self.bits >> OFFSET) & MASK as u32) != 0
368        };
369        PLLSAI1QENR { bits }
370    }
371    #[doc = "Bit 17 - SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)"]
372    #[inline]
373    pub fn pllsai1p(&self) -> PLLSAI1PR {
374        let bits = {
375            const MASK: bool = true;
376            const OFFSET: u8 = 17;
377            ((self.bits >> OFFSET) & MASK as u32) != 0
378        };
379        PLLSAI1PR { bits }
380    }
381    #[doc = "Bit 16 - SAI1PLL PLLSAI1CLK output enable"]
382    #[inline]
383    pub fn pllsai1pen(&self) -> PLLSAI1PENR {
384        let bits = {
385            const MASK: bool = true;
386            const OFFSET: u8 = 16;
387            ((self.bits >> OFFSET) & MASK as u32) != 0
388        };
389        PLLSAI1PENR { bits }
390    }
391    #[doc = "Bits 8:14 - SAI1PLL multiplication factor for VCO"]
392    #[inline]
393    pub fn pllsai1n(&self) -> PLLSAI1NR {
394        let bits = {
395            const MASK: u8 = 127;
396            const OFFSET: u8 = 8;
397            ((self.bits >> OFFSET) & MASK as u32) as u8
398        };
399        PLLSAI1NR { bits }
400    }
401    #[doc = "Bits 27:31 - PLLSAI1 division factor for PLLSAI1CLK"]
402    #[inline]
403    pub fn pllsai1pdiv(&self) -> PLLSAI1PDIVR {
404        let bits = {
405            const MASK: u8 = 31;
406            const OFFSET: u8 = 27;
407            ((self.bits >> OFFSET) & MASK as u32) as u8
408        };
409        PLLSAI1PDIVR { bits }
410    }
411}
412impl W {
413    #[doc = r" Reset value of the register"]
414    #[inline]
415    pub fn reset_value() -> W {
416        W { bits: 4096 }
417    }
418    #[doc = r" Writes raw bits to the register"]
419    #[inline]
420    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
421        self.bits = bits;
422        self
423    }
424    #[doc = "Bits 25:26 - PLLSAI1 division factor for PLLADC1CLK (ADC clock)"]
425    #[inline]
426    pub fn pllsai1r(&mut self) -> _PLLSAI1RW {
427        _PLLSAI1RW { w: self }
428    }
429    #[doc = "Bit 24 - PLLSAI1 PLLADC1CLK output enable"]
430    #[inline]
431    pub fn pllsai1ren(&mut self) -> _PLLSAI1RENW {
432        _PLLSAI1RENW { w: self }
433    }
434    #[doc = "Bits 21:22 - SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)"]
435    #[inline]
436    pub fn pllsai1q(&mut self) -> _PLLSAI1QW {
437        _PLLSAI1QW { w: self }
438    }
439    #[doc = "Bit 20 - SAI1PLL PLLUSB2CLK output enable"]
440    #[inline]
441    pub fn pllsai1qen(&mut self) -> _PLLSAI1QENW {
442        _PLLSAI1QENW { w: self }
443    }
444    #[doc = "Bit 17 - SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)"]
445    #[inline]
446    pub fn pllsai1p(&mut self) -> _PLLSAI1PW {
447        _PLLSAI1PW { w: self }
448    }
449    #[doc = "Bit 16 - SAI1PLL PLLSAI1CLK output enable"]
450    #[inline]
451    pub fn pllsai1pen(&mut self) -> _PLLSAI1PENW {
452        _PLLSAI1PENW { w: self }
453    }
454    #[doc = "Bits 8:14 - SAI1PLL multiplication factor for VCO"]
455    #[inline]
456    pub fn pllsai1n(&mut self) -> _PLLSAI1NW {
457        _PLLSAI1NW { w: self }
458    }
459    #[doc = "Bits 27:31 - PLLSAI1 division factor for PLLSAI1CLK"]
460    #[inline]
461    pub fn pllsai1pdiv(&mut self) -> _PLLSAI1PDIVW {
462        _PLLSAI1PDIVW { w: self }
463    }
464}
stm32l4x2_pac/rcc/pllsai1cfgr.rs

stm32l4x2_pac/rcc/
pllsai1cfgr.rs
