stm32l4x2_pac/rcc/
crrcr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CRRCR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct HSI48ONR {
47    bits: bool,
48}
49impl HSI48ONR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct HSI48RDYR {
68    bits: bool,
69}
70impl HSI48RDYR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct HSI48CALR {
89    bits: u16,
90}
91impl HSI48CALR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bits(&self) -> u16 {
95        self.bits
96    }
97}
98#[doc = r" Proxy"]
99pub struct _HSI48ONW<'a> {
100    w: &'a mut W,
101}
102impl<'a> _HSI48ONW<'a> {
103    #[doc = r" Sets the field bit"]
104    pub fn set_bit(self) -> &'a mut W {
105        self.bit(true)
106    }
107    #[doc = r" Clears the field bit"]
108    pub fn clear_bit(self) -> &'a mut W {
109        self.bit(false)
110    }
111    #[doc = r" Writes raw bits to the field"]
112    #[inline]
113    pub fn bit(self, value: bool) -> &'a mut W {
114        const MASK: bool = true;
115        const OFFSET: u8 = 0;
116        self.w.bits &= !((MASK as u32) << OFFSET);
117        self.w.bits |= ((value & MASK) as u32) << OFFSET;
118        self.w
119    }
120}
121impl R {
122    #[doc = r" Value of the register as raw bits"]
123    #[inline]
124    pub fn bits(&self) -> u32 {
125        self.bits
126    }
127    #[doc = "Bit 0 - HSI48 clock enable"]
128    #[inline]
129    pub fn hsi48on(&self) -> HSI48ONR {
130        let bits = {
131            const MASK: bool = true;
132            const OFFSET: u8 = 0;
133            ((self.bits >> OFFSET) & MASK as u32) != 0
134        };
135        HSI48ONR { bits }
136    }
137    #[doc = "Bit 1 - HSI48 clock ready flag"]
138    #[inline]
139    pub fn hsi48rdy(&self) -> HSI48RDYR {
140        let bits = {
141            const MASK: bool = true;
142            const OFFSET: u8 = 1;
143            ((self.bits >> OFFSET) & MASK as u32) != 0
144        };
145        HSI48RDYR { bits }
146    }
147    #[doc = "Bits 7:15 - HSI48 clock calibration"]
148    #[inline]
149    pub fn hsi48cal(&self) -> HSI48CALR {
150        let bits = {
151            const MASK: u16 = 511;
152            const OFFSET: u8 = 7;
153            ((self.bits >> OFFSET) & MASK as u32) as u16
154        };
155        HSI48CALR { bits }
156    }
157}
158impl W {
159    #[doc = r" Reset value of the register"]
160    #[inline]
161    pub fn reset_value() -> W {
162        W { bits: 201328128 }
163    }
164    #[doc = r" Writes raw bits to the register"]
165    #[inline]
166    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
167        self.bits = bits;
168        self
169    }
170    #[doc = "Bit 0 - HSI48 clock enable"]
171    #[inline]
172    pub fn hsi48on(&mut self) -> _HSI48ONW {
173        _HSI48ONW { w: self }
174    }
175}
stm32l4x2_pac/rcc/crrcr.rs

stm32l4x2_pac/rcc/
crrcr.rs
