stm32l4x2_pac/rcc/
cr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct PLLSAI1RDYR {
47    bits: bool,
48}
49impl PLLSAI1RDYR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct PLLSAI1ONR {
68    bits: bool,
69}
70impl PLLSAI1ONR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct PLLRDYR {
89    bits: bool,
90}
91impl PLLRDYR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bit(&self) -> bool {
95        self.bits
96    }
97    #[doc = r" Returns `true` if the bit is clear (0)"]
98    #[inline]
99    pub fn bit_is_clear(&self) -> bool {
100        !self.bit()
101    }
102    #[doc = r" Returns `true` if the bit is set (1)"]
103    #[inline]
104    pub fn bit_is_set(&self) -> bool {
105        self.bit()
106    }
107}
108#[doc = r" Value of the field"]
109pub struct PLLONR {
110    bits: bool,
111}
112impl PLLONR {
113    #[doc = r" Value of the field as raw bits"]
114    #[inline]
115    pub fn bit(&self) -> bool {
116        self.bits
117    }
118    #[doc = r" Returns `true` if the bit is clear (0)"]
119    #[inline]
120    pub fn bit_is_clear(&self) -> bool {
121        !self.bit()
122    }
123    #[doc = r" Returns `true` if the bit is set (1)"]
124    #[inline]
125    pub fn bit_is_set(&self) -> bool {
126        self.bit()
127    }
128}
129#[doc = r" Value of the field"]
130pub struct HSEBYPR {
131    bits: bool,
132}
133impl HSEBYPR {
134    #[doc = r" Value of the field as raw bits"]
135    #[inline]
136    pub fn bit(&self) -> bool {
137        self.bits
138    }
139    #[doc = r" Returns `true` if the bit is clear (0)"]
140    #[inline]
141    pub fn bit_is_clear(&self) -> bool {
142        !self.bit()
143    }
144    #[doc = r" Returns `true` if the bit is set (1)"]
145    #[inline]
146    pub fn bit_is_set(&self) -> bool {
147        self.bit()
148    }
149}
150#[doc = r" Value of the field"]
151pub struct HSERDYR {
152    bits: bool,
153}
154impl HSERDYR {
155    #[doc = r" Value of the field as raw bits"]
156    #[inline]
157    pub fn bit(&self) -> bool {
158        self.bits
159    }
160    #[doc = r" Returns `true` if the bit is clear (0)"]
161    #[inline]
162    pub fn bit_is_clear(&self) -> bool {
163        !self.bit()
164    }
165    #[doc = r" Returns `true` if the bit is set (1)"]
166    #[inline]
167    pub fn bit_is_set(&self) -> bool {
168        self.bit()
169    }
170}
171#[doc = r" Value of the field"]
172pub struct HSEONR {
173    bits: bool,
174}
175impl HSEONR {
176    #[doc = r" Value of the field as raw bits"]
177    #[inline]
178    pub fn bit(&self) -> bool {
179        self.bits
180    }
181    #[doc = r" Returns `true` if the bit is clear (0)"]
182    #[inline]
183    pub fn bit_is_clear(&self) -> bool {
184        !self.bit()
185    }
186    #[doc = r" Returns `true` if the bit is set (1)"]
187    #[inline]
188    pub fn bit_is_set(&self) -> bool {
189        self.bit()
190    }
191}
192#[doc = r" Value of the field"]
193pub struct HSIASFSR {
194    bits: bool,
195}
196impl HSIASFSR {
197    #[doc = r" Value of the field as raw bits"]
198    #[inline]
199    pub fn bit(&self) -> bool {
200        self.bits
201    }
202    #[doc = r" Returns `true` if the bit is clear (0)"]
203    #[inline]
204    pub fn bit_is_clear(&self) -> bool {
205        !self.bit()
206    }
207    #[doc = r" Returns `true` if the bit is set (1)"]
208    #[inline]
209    pub fn bit_is_set(&self) -> bool {
210        self.bit()
211    }
212}
213#[doc = r" Value of the field"]
214pub struct HSIRDYR {
215    bits: bool,
216}
217impl HSIRDYR {
218    #[doc = r" Value of the field as raw bits"]
219    #[inline]
220    pub fn bit(&self) -> bool {
221        self.bits
222    }
223    #[doc = r" Returns `true` if the bit is clear (0)"]
224    #[inline]
225    pub fn bit_is_clear(&self) -> bool {
226        !self.bit()
227    }
228    #[doc = r" Returns `true` if the bit is set (1)"]
229    #[inline]
230    pub fn bit_is_set(&self) -> bool {
231        self.bit()
232    }
233}
234#[doc = r" Value of the field"]
235pub struct HSIKERONR {
236    bits: bool,
237}
238impl HSIKERONR {
239    #[doc = r" Value of the field as raw bits"]
240    #[inline]
241    pub fn bit(&self) -> bool {
242        self.bits
243    }
244    #[doc = r" Returns `true` if the bit is clear (0)"]
245    #[inline]
246    pub fn bit_is_clear(&self) -> bool {
247        !self.bit()
248    }
249    #[doc = r" Returns `true` if the bit is set (1)"]
250    #[inline]
251    pub fn bit_is_set(&self) -> bool {
252        self.bit()
253    }
254}
255#[doc = r" Value of the field"]
256pub struct HSIONR {
257    bits: bool,
258}
259impl HSIONR {
260    #[doc = r" Value of the field as raw bits"]
261    #[inline]
262    pub fn bit(&self) -> bool {
263        self.bits
264    }
265    #[doc = r" Returns `true` if the bit is clear (0)"]
266    #[inline]
267    pub fn bit_is_clear(&self) -> bool {
268        !self.bit()
269    }
270    #[doc = r" Returns `true` if the bit is set (1)"]
271    #[inline]
272    pub fn bit_is_set(&self) -> bool {
273        self.bit()
274    }
275}
276#[doc = "Possible values of the field `MSIRANGE`"]
277#[derive(Clone, Copy, Debug, PartialEq)]
278pub enum MSIRANGER {
279    #[doc = "range 0 around 100 kHz"]
280    RANGE100K,
281    #[doc = "range 1 around 200 kHz"]
282    RANGE200K,
283    #[doc = "range 2 around 400 kHz"]
284    RANGE400K,
285    #[doc = "range 3 around 800 kHz"]
286    RANGE800K,
287    #[doc = "range 4 around 1 MHz"]
288    RANGE1M,
289    #[doc = "range 5 around 2 MHz"]
290    RANGE2M,
291    #[doc = "range 6 around 4 MHz"]
292    RANGE4M,
293    #[doc = "range 7 around 8 MHz"]
294    RANGE8M,
295    #[doc = "range 8 around 16 MHz"]
296    RANGE16M,
297    #[doc = "range 9 around 24 MHz"]
298    RANGE24M,
299    #[doc = "range 10 around 32 MHz"]
300    RANGE32M,
301    #[doc = "range 11 around 48 MHz"]
302    RANGE48M,
303    #[doc = r" Reserved"]
304    _Reserved(u8),
305}
306impl MSIRANGER {
307    #[doc = r" Value of the field as raw bits"]
308    #[inline]
309    pub fn bits(&self) -> u8 {
310        match *self {
311            MSIRANGER::RANGE100K => 0,
312            MSIRANGER::RANGE200K => 1,
313            MSIRANGER::RANGE400K => 2,
314            MSIRANGER::RANGE800K => 3,
315            MSIRANGER::RANGE1M => 4,
316            MSIRANGER::RANGE2M => 5,
317            MSIRANGER::RANGE4M => 6,
318            MSIRANGER::RANGE8M => 7,
319            MSIRANGER::RANGE16M => 8,
320            MSIRANGER::RANGE24M => 9,
321            MSIRANGER::RANGE32M => 10,
322            MSIRANGER::RANGE48M => 11,
323            MSIRANGER::_Reserved(bits) => bits,
324        }
325    }
326    #[allow(missing_docs)]
327    #[doc(hidden)]
328    #[inline]
329    pub fn _from(value: u8) -> MSIRANGER {
330        match value {
331            0 => MSIRANGER::RANGE100K,
332            1 => MSIRANGER::RANGE200K,
333            2 => MSIRANGER::RANGE400K,
334            3 => MSIRANGER::RANGE800K,
335            4 => MSIRANGER::RANGE1M,
336            5 => MSIRANGER::RANGE2M,
337            6 => MSIRANGER::RANGE4M,
338            7 => MSIRANGER::RANGE8M,
339            8 => MSIRANGER::RANGE16M,
340            9 => MSIRANGER::RANGE24M,
341            10 => MSIRANGER::RANGE32M,
342            11 => MSIRANGER::RANGE48M,
343            i => MSIRANGER::_Reserved(i),
344        }
345    }
346    #[doc = "Checks if the value of the field is `RANGE100K`"]
347    #[inline]
348    pub fn is_range100k(&self) -> bool {
349        *self == MSIRANGER::RANGE100K
350    }
351    #[doc = "Checks if the value of the field is `RANGE200K`"]
352    #[inline]
353    pub fn is_range200k(&self) -> bool {
354        *self == MSIRANGER::RANGE200K
355    }
356    #[doc = "Checks if the value of the field is `RANGE400K`"]
357    #[inline]
358    pub fn is_range400k(&self) -> bool {
359        *self == MSIRANGER::RANGE400K
360    }
361    #[doc = "Checks if the value of the field is `RANGE800K`"]
362    #[inline]
363    pub fn is_range800k(&self) -> bool {
364        *self == MSIRANGER::RANGE800K
365    }
366    #[doc = "Checks if the value of the field is `RANGE1M`"]
367    #[inline]
368    pub fn is_range1m(&self) -> bool {
369        *self == MSIRANGER::RANGE1M
370    }
371    #[doc = "Checks if the value of the field is `RANGE2M`"]
372    #[inline]
373    pub fn is_range2m(&self) -> bool {
374        *self == MSIRANGER::RANGE2M
375    }
376    #[doc = "Checks if the value of the field is `RANGE4M`"]
377    #[inline]
378    pub fn is_range4m(&self) -> bool {
379        *self == MSIRANGER::RANGE4M
380    }
381    #[doc = "Checks if the value of the field is `RANGE8M`"]
382    #[inline]
383    pub fn is_range8m(&self) -> bool {
384        *self == MSIRANGER::RANGE8M
385    }
386    #[doc = "Checks if the value of the field is `RANGE16M`"]
387    #[inline]
388    pub fn is_range16m(&self) -> bool {
389        *self == MSIRANGER::RANGE16M
390    }
391    #[doc = "Checks if the value of the field is `RANGE24M`"]
392    #[inline]
393    pub fn is_range24m(&self) -> bool {
394        *self == MSIRANGER::RANGE24M
395    }
396    #[doc = "Checks if the value of the field is `RANGE32M`"]
397    #[inline]
398    pub fn is_range32m(&self) -> bool {
399        *self == MSIRANGER::RANGE32M
400    }
401    #[doc = "Checks if the value of the field is `RANGE48M`"]
402    #[inline]
403    pub fn is_range48m(&self) -> bool {
404        *self == MSIRANGER::RANGE48M
405    }
406}
407#[doc = r" Value of the field"]
408pub struct MSIPLLENR {
409    bits: bool,
410}
411impl MSIPLLENR {
412    #[doc = r" Value of the field as raw bits"]
413    #[inline]
414    pub fn bit(&self) -> bool {
415        self.bits
416    }
417    #[doc = r" Returns `true` if the bit is clear (0)"]
418    #[inline]
419    pub fn bit_is_clear(&self) -> bool {
420        !self.bit()
421    }
422    #[doc = r" Returns `true` if the bit is set (1)"]
423    #[inline]
424    pub fn bit_is_set(&self) -> bool {
425        self.bit()
426    }
427}
428#[doc = r" Value of the field"]
429pub struct MSIRDYR {
430    bits: bool,
431}
432impl MSIRDYR {
433    #[doc = r" Value of the field as raw bits"]
434    #[inline]
435    pub fn bit(&self) -> bool {
436        self.bits
437    }
438    #[doc = r" Returns `true` if the bit is clear (0)"]
439    #[inline]
440    pub fn bit_is_clear(&self) -> bool {
441        !self.bit()
442    }
443    #[doc = r" Returns `true` if the bit is set (1)"]
444    #[inline]
445    pub fn bit_is_set(&self) -> bool {
446        self.bit()
447    }
448}
449#[doc = r" Value of the field"]
450pub struct MSIONR {
451    bits: bool,
452}
453impl MSIONR {
454    #[doc = r" Value of the field as raw bits"]
455    #[inline]
456    pub fn bit(&self) -> bool {
457        self.bits
458    }
459    #[doc = r" Returns `true` if the bit is clear (0)"]
460    #[inline]
461    pub fn bit_is_clear(&self) -> bool {
462        !self.bit()
463    }
464    #[doc = r" Returns `true` if the bit is set (1)"]
465    #[inline]
466    pub fn bit_is_set(&self) -> bool {
467        self.bit()
468    }
469}
470#[doc = r" Proxy"]
471pub struct _PLLSAI1ONW<'a> {
472    w: &'a mut W,
473}
474impl<'a> _PLLSAI1ONW<'a> {
475    #[doc = r" Sets the field bit"]
476    pub fn set_bit(self) -> &'a mut W {
477        self.bit(true)
478    }
479    #[doc = r" Clears the field bit"]
480    pub fn clear_bit(self) -> &'a mut W {
481        self.bit(false)
482    }
483    #[doc = r" Writes raw bits to the field"]
484    #[inline]
485    pub fn bit(self, value: bool) -> &'a mut W {
486        const MASK: bool = true;
487        const OFFSET: u8 = 26;
488        self.w.bits &= !((MASK as u32) << OFFSET);
489        self.w.bits |= ((value & MASK) as u32) << OFFSET;
490        self.w
491    }
492}
493#[doc = r" Proxy"]
494pub struct _PLLONW<'a> {
495    w: &'a mut W,
496}
497impl<'a> _PLLONW<'a> {
498    #[doc = r" Sets the field bit"]
499    pub fn set_bit(self) -> &'a mut W {
500        self.bit(true)
501    }
502    #[doc = r" Clears the field bit"]
503    pub fn clear_bit(self) -> &'a mut W {
504        self.bit(false)
505    }
506    #[doc = r" Writes raw bits to the field"]
507    #[inline]
508    pub fn bit(self, value: bool) -> &'a mut W {
509        const MASK: bool = true;
510        const OFFSET: u8 = 24;
511        self.w.bits &= !((MASK as u32) << OFFSET);
512        self.w.bits |= ((value & MASK) as u32) << OFFSET;
513        self.w
514    }
515}
516#[doc = r" Proxy"]
517pub struct _CSSONW<'a> {
518    w: &'a mut W,
519}
520impl<'a> _CSSONW<'a> {
521    #[doc = r" Sets the field bit"]
522    pub fn set_bit(self) -> &'a mut W {
523        self.bit(true)
524    }
525    #[doc = r" Clears the field bit"]
526    pub fn clear_bit(self) -> &'a mut W {
527        self.bit(false)
528    }
529    #[doc = r" Writes raw bits to the field"]
530    #[inline]
531    pub fn bit(self, value: bool) -> &'a mut W {
532        const MASK: bool = true;
533        const OFFSET: u8 = 19;
534        self.w.bits &= !((MASK as u32) << OFFSET);
535        self.w.bits |= ((value & MASK) as u32) << OFFSET;
536        self.w
537    }
538}
539#[doc = r" Proxy"]
540pub struct _HSEBYPW<'a> {
541    w: &'a mut W,
542}
543impl<'a> _HSEBYPW<'a> {
544    #[doc = r" Sets the field bit"]
545    pub fn set_bit(self) -> &'a mut W {
546        self.bit(true)
547    }
548    #[doc = r" Clears the field bit"]
549    pub fn clear_bit(self) -> &'a mut W {
550        self.bit(false)
551    }
552    #[doc = r" Writes raw bits to the field"]
553    #[inline]
554    pub fn bit(self, value: bool) -> &'a mut W {
555        const MASK: bool = true;
556        const OFFSET: u8 = 18;
557        self.w.bits &= !((MASK as u32) << OFFSET);
558        self.w.bits |= ((value & MASK) as u32) << OFFSET;
559        self.w
560    }
561}
562#[doc = r" Proxy"]
563pub struct _HSEONW<'a> {
564    w: &'a mut W,
565}
566impl<'a> _HSEONW<'a> {
567    #[doc = r" Sets the field bit"]
568    pub fn set_bit(self) -> &'a mut W {
569        self.bit(true)
570    }
571    #[doc = r" Clears the field bit"]
572    pub fn clear_bit(self) -> &'a mut W {
573        self.bit(false)
574    }
575    #[doc = r" Writes raw bits to the field"]
576    #[inline]
577    pub fn bit(self, value: bool) -> &'a mut W {
578        const MASK: bool = true;
579        const OFFSET: u8 = 16;
580        self.w.bits &= !((MASK as u32) << OFFSET);
581        self.w.bits |= ((value & MASK) as u32) << OFFSET;
582        self.w
583    }
584}
585#[doc = r" Proxy"]
586pub struct _HSIASFSW<'a> {
587    w: &'a mut W,
588}
589impl<'a> _HSIASFSW<'a> {
590    #[doc = r" Sets the field bit"]
591    pub fn set_bit(self) -> &'a mut W {
592        self.bit(true)
593    }
594    #[doc = r" Clears the field bit"]
595    pub fn clear_bit(self) -> &'a mut W {
596        self.bit(false)
597    }
598    #[doc = r" Writes raw bits to the field"]
599    #[inline]
600    pub fn bit(self, value: bool) -> &'a mut W {
601        const MASK: bool = true;
602        const OFFSET: u8 = 11;
603        self.w.bits &= !((MASK as u32) << OFFSET);
604        self.w.bits |= ((value & MASK) as u32) << OFFSET;
605        self.w
606    }
607}
608#[doc = r" Proxy"]
609pub struct _HSIKERONW<'a> {
610    w: &'a mut W,
611}
612impl<'a> _HSIKERONW<'a> {
613    #[doc = r" Sets the field bit"]
614    pub fn set_bit(self) -> &'a mut W {
615        self.bit(true)
616    }
617    #[doc = r" Clears the field bit"]
618    pub fn clear_bit(self) -> &'a mut W {
619        self.bit(false)
620    }
621    #[doc = r" Writes raw bits to the field"]
622    #[inline]
623    pub fn bit(self, value: bool) -> &'a mut W {
624        const MASK: bool = true;
625        const OFFSET: u8 = 9;
626        self.w.bits &= !((MASK as u32) << OFFSET);
627        self.w.bits |= ((value & MASK) as u32) << OFFSET;
628        self.w
629    }
630}
631#[doc = r" Proxy"]
632pub struct _HSIONW<'a> {
633    w: &'a mut W,
634}
635impl<'a> _HSIONW<'a> {
636    #[doc = r" Sets the field bit"]
637    pub fn set_bit(self) -> &'a mut W {
638        self.bit(true)
639    }
640    #[doc = r" Clears the field bit"]
641    pub fn clear_bit(self) -> &'a mut W {
642        self.bit(false)
643    }
644    #[doc = r" Writes raw bits to the field"]
645    #[inline]
646    pub fn bit(self, value: bool) -> &'a mut W {
647        const MASK: bool = true;
648        const OFFSET: u8 = 8;
649        self.w.bits &= !((MASK as u32) << OFFSET);
650        self.w.bits |= ((value & MASK) as u32) << OFFSET;
651        self.w
652    }
653}
654#[doc = "Values that can be written to the field `MSIRANGE`"]
655pub enum MSIRANGEW {
656    #[doc = "range 0 around 100 kHz"]
657    RANGE100K,
658    #[doc = "range 1 around 200 kHz"]
659    RANGE200K,
660    #[doc = "range 2 around 400 kHz"]
661    RANGE400K,
662    #[doc = "range 3 around 800 kHz"]
663    RANGE800K,
664    #[doc = "range 4 around 1 MHz"]
665    RANGE1M,
666    #[doc = "range 5 around 2 MHz"]
667    RANGE2M,
668    #[doc = "range 6 around 4 MHz"]
669    RANGE4M,
670    #[doc = "range 7 around 8 MHz"]
671    RANGE8M,
672    #[doc = "range 8 around 16 MHz"]
673    RANGE16M,
674    #[doc = "range 9 around 24 MHz"]
675    RANGE24M,
676    #[doc = "range 10 around 32 MHz"]
677    RANGE32M,
678    #[doc = "range 11 around 48 MHz"]
679    RANGE48M,
680}
681impl MSIRANGEW {
682    #[allow(missing_docs)]
683    #[doc(hidden)]
684    #[inline]
685    pub fn _bits(&self) -> u8 {
686        match *self {
687            MSIRANGEW::RANGE100K => 0,
688            MSIRANGEW::RANGE200K => 1,
689            MSIRANGEW::RANGE400K => 2,
690            MSIRANGEW::RANGE800K => 3,
691            MSIRANGEW::RANGE1M => 4,
692            MSIRANGEW::RANGE2M => 5,
693            MSIRANGEW::RANGE4M => 6,
694            MSIRANGEW::RANGE8M => 7,
695            MSIRANGEW::RANGE16M => 8,
696            MSIRANGEW::RANGE24M => 9,
697            MSIRANGEW::RANGE32M => 10,
698            MSIRANGEW::RANGE48M => 11,
699        }
700    }
701}
702#[doc = r" Proxy"]
703pub struct _MSIRANGEW<'a> {
704    w: &'a mut W,
705}
706impl<'a> _MSIRANGEW<'a> {
707    #[doc = r" Writes `variant` to the field"]
708    #[inline]
709    pub fn variant(self, variant: MSIRANGEW) -> &'a mut W {
710        unsafe { self.bits(variant._bits()) }
711    }
712    #[doc = "range 0 around 100 kHz"]
713    #[inline]
714    pub fn range100k(self) -> &'a mut W {
715        self.variant(MSIRANGEW::RANGE100K)
716    }
717    #[doc = "range 1 around 200 kHz"]
718    #[inline]
719    pub fn range200k(self) -> &'a mut W {
720        self.variant(MSIRANGEW::RANGE200K)
721    }
722    #[doc = "range 2 around 400 kHz"]
723    #[inline]
724    pub fn range400k(self) -> &'a mut W {
725        self.variant(MSIRANGEW::RANGE400K)
726    }
727    #[doc = "range 3 around 800 kHz"]
728    #[inline]
729    pub fn range800k(self) -> &'a mut W {
730        self.variant(MSIRANGEW::RANGE800K)
731    }
732    #[doc = "range 4 around 1 MHz"]
733    #[inline]
734    pub fn range1m(self) -> &'a mut W {
735        self.variant(MSIRANGEW::RANGE1M)
736    }
737    #[doc = "range 5 around 2 MHz"]
738    #[inline]
739    pub fn range2m(self) -> &'a mut W {
740        self.variant(MSIRANGEW::RANGE2M)
741    }
742    #[doc = "range 6 around 4 MHz"]
743    #[inline]
744    pub fn range4m(self) -> &'a mut W {
745        self.variant(MSIRANGEW::RANGE4M)
746    }
747    #[doc = "range 7 around 8 MHz"]
748    #[inline]
749    pub fn range8m(self) -> &'a mut W {
750        self.variant(MSIRANGEW::RANGE8M)
751    }
752    #[doc = "range 8 around 16 MHz"]
753    #[inline]
754    pub fn range16m(self) -> &'a mut W {
755        self.variant(MSIRANGEW::RANGE16M)
756    }
757    #[doc = "range 9 around 24 MHz"]
758    #[inline]
759    pub fn range24m(self) -> &'a mut W {
760        self.variant(MSIRANGEW::RANGE24M)
761    }
762    #[doc = "range 10 around 32 MHz"]
763    #[inline]
764    pub fn range32m(self) -> &'a mut W {
765        self.variant(MSIRANGEW::RANGE32M)
766    }
767    #[doc = "range 11 around 48 MHz"]
768    #[inline]
769    pub fn range48m(self) -> &'a mut W {
770        self.variant(MSIRANGEW::RANGE48M)
771    }
772    #[doc = r" Writes raw bits to the field"]
773    #[inline]
774    pub unsafe fn bits(self, value: u8) -> &'a mut W {
775        const MASK: u8 = 15;
776        const OFFSET: u8 = 4;
777        self.w.bits &= !((MASK as u32) << OFFSET);
778        self.w.bits |= ((value & MASK) as u32) << OFFSET;
779        self.w
780    }
781}
782#[doc = r" Proxy"]
783pub struct _MSIRGSELW<'a> {
784    w: &'a mut W,
785}
786impl<'a> _MSIRGSELW<'a> {
787    #[doc = r" Sets the field bit"]
788    pub fn set_bit(self) -> &'a mut W {
789        self.bit(true)
790    }
791    #[doc = r" Clears the field bit"]
792    pub fn clear_bit(self) -> &'a mut W {
793        self.bit(false)
794    }
795    #[doc = r" Writes raw bits to the field"]
796    #[inline]
797    pub fn bit(self, value: bool) -> &'a mut W {
798        const MASK: bool = true;
799        const OFFSET: u8 = 3;
800        self.w.bits &= !((MASK as u32) << OFFSET);
801        self.w.bits |= ((value & MASK) as u32) << OFFSET;
802        self.w
803    }
804}
805#[doc = r" Proxy"]
806pub struct _MSIPLLENW<'a> {
807    w: &'a mut W,
808}
809impl<'a> _MSIPLLENW<'a> {
810    #[doc = r" Sets the field bit"]
811    pub fn set_bit(self) -> &'a mut W {
812        self.bit(true)
813    }
814    #[doc = r" Clears the field bit"]
815    pub fn clear_bit(self) -> &'a mut W {
816        self.bit(false)
817    }
818    #[doc = r" Writes raw bits to the field"]
819    #[inline]
820    pub fn bit(self, value: bool) -> &'a mut W {
821        const MASK: bool = true;
822        const OFFSET: u8 = 2;
823        self.w.bits &= !((MASK as u32) << OFFSET);
824        self.w.bits |= ((value & MASK) as u32) << OFFSET;
825        self.w
826    }
827}
828#[doc = r" Proxy"]
829pub struct _MSIONW<'a> {
830    w: &'a mut W,
831}
832impl<'a> _MSIONW<'a> {
833    #[doc = r" Sets the field bit"]
834    pub fn set_bit(self) -> &'a mut W {
835        self.bit(true)
836    }
837    #[doc = r" Clears the field bit"]
838    pub fn clear_bit(self) -> &'a mut W {
839        self.bit(false)
840    }
841    #[doc = r" Writes raw bits to the field"]
842    #[inline]
843    pub fn bit(self, value: bool) -> &'a mut W {
844        const MASK: bool = true;
845        const OFFSET: u8 = 0;
846        self.w.bits &= !((MASK as u32) << OFFSET);
847        self.w.bits |= ((value & MASK) as u32) << OFFSET;
848        self.w
849    }
850}
851impl R {
852    #[doc = r" Value of the register as raw bits"]
853    #[inline]
854    pub fn bits(&self) -> u32 {
855        self.bits
856    }
857    #[doc = "Bit 27 - SAI1 PLL clock ready flag"]
858    #[inline]
859    pub fn pllsai1rdy(&self) -> PLLSAI1RDYR {
860        let bits = {
861            const MASK: bool = true;
862            const OFFSET: u8 = 27;
863            ((self.bits >> OFFSET) & MASK as u32) != 0
864        };
865        PLLSAI1RDYR { bits }
866    }
867    #[doc = "Bit 26 - SAI1 PLL enable"]
868    #[inline]
869    pub fn pllsai1on(&self) -> PLLSAI1ONR {
870        let bits = {
871            const MASK: bool = true;
872            const OFFSET: u8 = 26;
873            ((self.bits >> OFFSET) & MASK as u32) != 0
874        };
875        PLLSAI1ONR { bits }
876    }
877    #[doc = "Bit 25 - Main PLL clock ready flag"]
878    #[inline]
879    pub fn pllrdy(&self) -> PLLRDYR {
880        let bits = {
881            const MASK: bool = true;
882            const OFFSET: u8 = 25;
883            ((self.bits >> OFFSET) & MASK as u32) != 0
884        };
885        PLLRDYR { bits }
886    }
887    #[doc = "Bit 24 - Main PLL enable"]
888    #[inline]
889    pub fn pllon(&self) -> PLLONR {
890        let bits = {
891            const MASK: bool = true;
892            const OFFSET: u8 = 24;
893            ((self.bits >> OFFSET) & MASK as u32) != 0
894        };
895        PLLONR { bits }
896    }
897    #[doc = "Bit 18 - HSE crystal oscillator bypass"]
898    #[inline]
899    pub fn hsebyp(&self) -> HSEBYPR {
900        let bits = {
901            const MASK: bool = true;
902            const OFFSET: u8 = 18;
903            ((self.bits >> OFFSET) & MASK as u32) != 0
904        };
905        HSEBYPR { bits }
906    }
907    #[doc = "Bit 17 - HSE clock ready flag"]
908    #[inline]
909    pub fn hserdy(&self) -> HSERDYR {
910        let bits = {
911            const MASK: bool = true;
912            const OFFSET: u8 = 17;
913            ((self.bits >> OFFSET) & MASK as u32) != 0
914        };
915        HSERDYR { bits }
916    }
917    #[doc = "Bit 16 - HSE clock enable"]
918    #[inline]
919    pub fn hseon(&self) -> HSEONR {
920        let bits = {
921            const MASK: bool = true;
922            const OFFSET: u8 = 16;
923            ((self.bits >> OFFSET) & MASK as u32) != 0
924        };
925        HSEONR { bits }
926    }
927    #[doc = "Bit 11 - HSI automatic start from Stop"]
928    #[inline]
929    pub fn hsiasfs(&self) -> HSIASFSR {
930        let bits = {
931            const MASK: bool = true;
932            const OFFSET: u8 = 11;
933            ((self.bits >> OFFSET) & MASK as u32) != 0
934        };
935        HSIASFSR { bits }
936    }
937    #[doc = "Bit 10 - HSI clock ready flag"]
938    #[inline]
939    pub fn hsirdy(&self) -> HSIRDYR {
940        let bits = {
941            const MASK: bool = true;
942            const OFFSET: u8 = 10;
943            ((self.bits >> OFFSET) & MASK as u32) != 0
944        };
945        HSIRDYR { bits }
946    }
947    #[doc = "Bit 9 - HSI always enable for peripheral kernels"]
948    #[inline]
949    pub fn hsikeron(&self) -> HSIKERONR {
950        let bits = {
951            const MASK: bool = true;
952            const OFFSET: u8 = 9;
953            ((self.bits >> OFFSET) & MASK as u32) != 0
954        };
955        HSIKERONR { bits }
956    }
957    #[doc = "Bit 8 - HSI clock enable"]
958    #[inline]
959    pub fn hsion(&self) -> HSIONR {
960        let bits = {
961            const MASK: bool = true;
962            const OFFSET: u8 = 8;
963            ((self.bits >> OFFSET) & MASK as u32) != 0
964        };
965        HSIONR { bits }
966    }
967    #[doc = "Bits 4:7 - MSI clock ranges"]
968    #[inline]
969    pub fn msirange(&self) -> MSIRANGER {
970        MSIRANGER::_from({
971            const MASK: u8 = 15;
972            const OFFSET: u8 = 4;
973            ((self.bits >> OFFSET) & MASK as u32) as u8
974        })
975    }
976    #[doc = "Bit 2 - MSI clock PLL enable"]
977    #[inline]
978    pub fn msipllen(&self) -> MSIPLLENR {
979        let bits = {
980            const MASK: bool = true;
981            const OFFSET: u8 = 2;
982            ((self.bits >> OFFSET) & MASK as u32) != 0
983        };
984        MSIPLLENR { bits }
985    }
986    #[doc = "Bit 1 - MSI clock ready flag"]
987    #[inline]
988    pub fn msirdy(&self) -> MSIRDYR {
989        let bits = {
990            const MASK: bool = true;
991            const OFFSET: u8 = 1;
992            ((self.bits >> OFFSET) & MASK as u32) != 0
993        };
994        MSIRDYR { bits }
995    }
996    #[doc = "Bit 0 - MSI clock enable"]
997    #[inline]
998    pub fn msion(&self) -> MSIONR {
999        let bits = {
1000            const MASK: bool = true;
1001            const OFFSET: u8 = 0;
1002            ((self.bits >> OFFSET) & MASK as u32) != 0
1003        };
1004        MSIONR { bits }
1005    }
1006}
1007impl W {
1008    #[doc = r" Reset value of the register"]
1009    #[inline]
1010    pub fn reset_value() -> W {
1011        W { bits: 99 }
1012    }
1013    #[doc = r" Writes raw bits to the register"]
1014    #[inline]
1015    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1016        self.bits = bits;
1017        self
1018    }
1019    #[doc = "Bit 26 - SAI1 PLL enable"]
1020    #[inline]
1021    pub fn pllsai1on(&mut self) -> _PLLSAI1ONW {
1022        _PLLSAI1ONW { w: self }
1023    }
1024    #[doc = "Bit 24 - Main PLL enable"]
1025    #[inline]
1026    pub fn pllon(&mut self) -> _PLLONW {
1027        _PLLONW { w: self }
1028    }
1029    #[doc = "Bit 19 - Clock security system enable"]
1030    #[inline]
1031    pub fn csson(&mut self) -> _CSSONW {
1032        _CSSONW { w: self }
1033    }
1034    #[doc = "Bit 18 - HSE crystal oscillator bypass"]
1035    #[inline]
1036    pub fn hsebyp(&mut self) -> _HSEBYPW {
1037        _HSEBYPW { w: self }
1038    }
1039    #[doc = "Bit 16 - HSE clock enable"]
1040    #[inline]
1041    pub fn hseon(&mut self) -> _HSEONW {
1042        _HSEONW { w: self }
1043    }
1044    #[doc = "Bit 11 - HSI automatic start from Stop"]
1045    #[inline]
1046    pub fn hsiasfs(&mut self) -> _HSIASFSW {
1047        _HSIASFSW { w: self }
1048    }
1049    #[doc = "Bit 9 - HSI always enable for peripheral kernels"]
1050    #[inline]
1051    pub fn hsikeron(&mut self) -> _HSIKERONW {
1052        _HSIKERONW { w: self }
1053    }
1054    #[doc = "Bit 8 - HSI clock enable"]
1055    #[inline]
1056    pub fn hsion(&mut self) -> _HSIONW {
1057        _HSIONW { w: self }
1058    }
1059    #[doc = "Bits 4:7 - MSI clock ranges"]
1060    #[inline]
1061    pub fn msirange(&mut self) -> _MSIRANGEW {
1062        _MSIRANGEW { w: self }
1063    }
1064    #[doc = "Bit 3 - MSI clock range selection"]
1065    #[inline]
1066    pub fn msirgsel(&mut self) -> _MSIRGSELW {
1067        _MSIRGSELW { w: self }
1068    }
1069    #[doc = "Bit 2 - MSI clock PLL enable"]
1070    #[inline]
1071    pub fn msipllen(&mut self) -> _MSIPLLENW {
1072        _MSIPLLENW { w: self }
1073    }
1074    #[doc = "Bit 0 - MSI clock enable"]
1075    #[inline]
1076    pub fn msion(&mut self) -> _MSIONW {
1077        _MSIONW { w: self }
1078    }
1079}
stm32l4x2_pac/rcc/cr.rs

stm32l4x2_pac/rcc/
cr.rs
