1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CCR6 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `MEM2MEM`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum MEM2MEMR {
48 #[doc = "Memory to memory mode disabled"]
49 DISABLED,
50 #[doc = "Memory to memory mode enabled"]
51 ENABLED,
52}
53impl MEM2MEMR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 MEM2MEMR::DISABLED => false,
69 MEM2MEMR::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> MEM2MEMR {
76 match value {
77 false => MEM2MEMR::DISABLED,
78 true => MEM2MEMR::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == MEM2MEMR::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == MEM2MEMR::ENABLED
90 }
91}
92#[doc = "Possible values of the field `PL`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum PLR {
95 #[doc = "Low priority"]
96 LOW,
97 #[doc = "Medium priority"]
98 MEDIUM,
99 #[doc = "High priority"]
100 HIGH,
101 #[doc = "Very high priority"]
102 VERYHIGH,
103}
104impl PLR {
105 #[doc = r" Value of the field as raw bits"]
106 #[inline]
107 pub fn bits(&self) -> u8 {
108 match *self {
109 PLR::LOW => 0,
110 PLR::MEDIUM => 1,
111 PLR::HIGH => 2,
112 PLR::VERYHIGH => 3,
113 }
114 }
115 #[allow(missing_docs)]
116 #[doc(hidden)]
117 #[inline]
118 pub fn _from(value: u8) -> PLR {
119 match value {
120 0 => PLR::LOW,
121 1 => PLR::MEDIUM,
122 2 => PLR::HIGH,
123 3 => PLR::VERYHIGH,
124 _ => unreachable!(),
125 }
126 }
127 #[doc = "Checks if the value of the field is `LOW`"]
128 #[inline]
129 pub fn is_low(&self) -> bool {
130 *self == PLR::LOW
131 }
132 #[doc = "Checks if the value of the field is `MEDIUM`"]
133 #[inline]
134 pub fn is_medium(&self) -> bool {
135 *self == PLR::MEDIUM
136 }
137 #[doc = "Checks if the value of the field is `HIGH`"]
138 #[inline]
139 pub fn is_high(&self) -> bool {
140 *self == PLR::HIGH
141 }
142 #[doc = "Checks if the value of the field is `VERYHIGH`"]
143 #[inline]
144 pub fn is_very_high(&self) -> bool {
145 *self == PLR::VERYHIGH
146 }
147}
148#[doc = "Possible values of the field `MSIZE`"]
149#[derive(Clone, Copy, Debug, PartialEq)]
150pub enum MSIZER {
151 #[doc = "8-bit size"]
152 BIT8,
153 #[doc = "16-bit size"]
154 BIT16,
155 #[doc = "32-bit size"]
156 BIT32,
157 #[doc = r" Reserved"]
158 _Reserved(u8),
159}
160impl MSIZER {
161 #[doc = r" Value of the field as raw bits"]
162 #[inline]
163 pub fn bits(&self) -> u8 {
164 match *self {
165 MSIZER::BIT8 => 0,
166 MSIZER::BIT16 => 1,
167 MSIZER::BIT32 => 2,
168 MSIZER::_Reserved(bits) => bits,
169 }
170 }
171 #[allow(missing_docs)]
172 #[doc(hidden)]
173 #[inline]
174 pub fn _from(value: u8) -> MSIZER {
175 match value {
176 0 => MSIZER::BIT8,
177 1 => MSIZER::BIT16,
178 2 => MSIZER::BIT32,
179 i => MSIZER::_Reserved(i),
180 }
181 }
182 #[doc = "Checks if the value of the field is `BIT8`"]
183 #[inline]
184 pub fn is_bit8(&self) -> bool {
185 *self == MSIZER::BIT8
186 }
187 #[doc = "Checks if the value of the field is `BIT16`"]
188 #[inline]
189 pub fn is_bit16(&self) -> bool {
190 *self == MSIZER::BIT16
191 }
192 #[doc = "Checks if the value of the field is `BIT32`"]
193 #[inline]
194 pub fn is_bit32(&self) -> bool {
195 *self == MSIZER::BIT32
196 }
197}
198#[doc = "Possible values of the field `PSIZE`"]
199pub type PSIZER = MSIZER;
200#[doc = "Possible values of the field `MINC`"]
201#[derive(Clone, Copy, Debug, PartialEq)]
202pub enum MINCR {
203 #[doc = "Increment mode disabled"]
204 DISABLED,
205 #[doc = "Increment mode enabled"]
206 ENABLED,
207}
208impl MINCR {
209 #[doc = r" Returns `true` if the bit is clear (0)"]
210 #[inline]
211 pub fn bit_is_clear(&self) -> bool {
212 !self.bit()
213 }
214 #[doc = r" Returns `true` if the bit is set (1)"]
215 #[inline]
216 pub fn bit_is_set(&self) -> bool {
217 self.bit()
218 }
219 #[doc = r" Value of the field as raw bits"]
220 #[inline]
221 pub fn bit(&self) -> bool {
222 match *self {
223 MINCR::DISABLED => false,
224 MINCR::ENABLED => true,
225 }
226 }
227 #[allow(missing_docs)]
228 #[doc(hidden)]
229 #[inline]
230 pub fn _from(value: bool) -> MINCR {
231 match value {
232 false => MINCR::DISABLED,
233 true => MINCR::ENABLED,
234 }
235 }
236 #[doc = "Checks if the value of the field is `DISABLED`"]
237 #[inline]
238 pub fn is_disabled(&self) -> bool {
239 *self == MINCR::DISABLED
240 }
241 #[doc = "Checks if the value of the field is `ENABLED`"]
242 #[inline]
243 pub fn is_enabled(&self) -> bool {
244 *self == MINCR::ENABLED
245 }
246}
247#[doc = "Possible values of the field `PINC`"]
248pub type PINCR = MINCR;
249#[doc = "Possible values of the field `CIRC`"]
250#[derive(Clone, Copy, Debug, PartialEq)]
251pub enum CIRCR {
252 #[doc = "Circular buffer disabled"]
253 DISABLED,
254 #[doc = "Circular buffer enabled"]
255 ENABLED,
256}
257impl CIRCR {
258 #[doc = r" Returns `true` if the bit is clear (0)"]
259 #[inline]
260 pub fn bit_is_clear(&self) -> bool {
261 !self.bit()
262 }
263 #[doc = r" Returns `true` if the bit is set (1)"]
264 #[inline]
265 pub fn bit_is_set(&self) -> bool {
266 self.bit()
267 }
268 #[doc = r" Value of the field as raw bits"]
269 #[inline]
270 pub fn bit(&self) -> bool {
271 match *self {
272 CIRCR::DISABLED => false,
273 CIRCR::ENABLED => true,
274 }
275 }
276 #[allow(missing_docs)]
277 #[doc(hidden)]
278 #[inline]
279 pub fn _from(value: bool) -> CIRCR {
280 match value {
281 false => CIRCR::DISABLED,
282 true => CIRCR::ENABLED,
283 }
284 }
285 #[doc = "Checks if the value of the field is `DISABLED`"]
286 #[inline]
287 pub fn is_disabled(&self) -> bool {
288 *self == CIRCR::DISABLED
289 }
290 #[doc = "Checks if the value of the field is `ENABLED`"]
291 #[inline]
292 pub fn is_enabled(&self) -> bool {
293 *self == CIRCR::ENABLED
294 }
295}
296#[doc = "Possible values of the field `DIR`"]
297#[derive(Clone, Copy, Debug, PartialEq)]
298pub enum DIRR {
299 #[doc = "Read from peripheral"]
300 FROMPERIPHERAL,
301 #[doc = "Read from memory"]
302 FROMMEMORY,
303}
304impl DIRR {
305 #[doc = r" Returns `true` if the bit is clear (0)"]
306 #[inline]
307 pub fn bit_is_clear(&self) -> bool {
308 !self.bit()
309 }
310 #[doc = r" Returns `true` if the bit is set (1)"]
311 #[inline]
312 pub fn bit_is_set(&self) -> bool {
313 self.bit()
314 }
315 #[doc = r" Value of the field as raw bits"]
316 #[inline]
317 pub fn bit(&self) -> bool {
318 match *self {
319 DIRR::FROMPERIPHERAL => false,
320 DIRR::FROMMEMORY => true,
321 }
322 }
323 #[allow(missing_docs)]
324 #[doc(hidden)]
325 #[inline]
326 pub fn _from(value: bool) -> DIRR {
327 match value {
328 false => DIRR::FROMPERIPHERAL,
329 true => DIRR::FROMMEMORY,
330 }
331 }
332 #[doc = "Checks if the value of the field is `FROMPERIPHERAL`"]
333 #[inline]
334 pub fn is_from_peripheral(&self) -> bool {
335 *self == DIRR::FROMPERIPHERAL
336 }
337 #[doc = "Checks if the value of the field is `FROMMEMORY`"]
338 #[inline]
339 pub fn is_from_memory(&self) -> bool {
340 *self == DIRR::FROMMEMORY
341 }
342}
343#[doc = "Possible values of the field `TEIE`"]
344#[derive(Clone, Copy, Debug, PartialEq)]
345pub enum TEIER {
346 #[doc = "Transfer Error interrupt disabled"]
347 DISABLED,
348 #[doc = "Transfer Error interrupt enabled"]
349 ENABLED,
350}
351impl TEIER {
352 #[doc = r" Returns `true` if the bit is clear (0)"]
353 #[inline]
354 pub fn bit_is_clear(&self) -> bool {
355 !self.bit()
356 }
357 #[doc = r" Returns `true` if the bit is set (1)"]
358 #[inline]
359 pub fn bit_is_set(&self) -> bool {
360 self.bit()
361 }
362 #[doc = r" Value of the field as raw bits"]
363 #[inline]
364 pub fn bit(&self) -> bool {
365 match *self {
366 TEIER::DISABLED => false,
367 TEIER::ENABLED => true,
368 }
369 }
370 #[allow(missing_docs)]
371 #[doc(hidden)]
372 #[inline]
373 pub fn _from(value: bool) -> TEIER {
374 match value {
375 false => TEIER::DISABLED,
376 true => TEIER::ENABLED,
377 }
378 }
379 #[doc = "Checks if the value of the field is `DISABLED`"]
380 #[inline]
381 pub fn is_disabled(&self) -> bool {
382 *self == TEIER::DISABLED
383 }
384 #[doc = "Checks if the value of the field is `ENABLED`"]
385 #[inline]
386 pub fn is_enabled(&self) -> bool {
387 *self == TEIER::ENABLED
388 }
389}
390#[doc = "Possible values of the field `HTIE`"]
391#[derive(Clone, Copy, Debug, PartialEq)]
392pub enum HTIER {
393 #[doc = "Half Transfer interrupt disabled"]
394 DISABLED,
395 #[doc = "Half Transfer interrupt enabled"]
396 ENABLED,
397}
398impl HTIER {
399 #[doc = r" Returns `true` if the bit is clear (0)"]
400 #[inline]
401 pub fn bit_is_clear(&self) -> bool {
402 !self.bit()
403 }
404 #[doc = r" Returns `true` if the bit is set (1)"]
405 #[inline]
406 pub fn bit_is_set(&self) -> bool {
407 self.bit()
408 }
409 #[doc = r" Value of the field as raw bits"]
410 #[inline]
411 pub fn bit(&self) -> bool {
412 match *self {
413 HTIER::DISABLED => false,
414 HTIER::ENABLED => true,
415 }
416 }
417 #[allow(missing_docs)]
418 #[doc(hidden)]
419 #[inline]
420 pub fn _from(value: bool) -> HTIER {
421 match value {
422 false => HTIER::DISABLED,
423 true => HTIER::ENABLED,
424 }
425 }
426 #[doc = "Checks if the value of the field is `DISABLED`"]
427 #[inline]
428 pub fn is_disabled(&self) -> bool {
429 *self == HTIER::DISABLED
430 }
431 #[doc = "Checks if the value of the field is `ENABLED`"]
432 #[inline]
433 pub fn is_enabled(&self) -> bool {
434 *self == HTIER::ENABLED
435 }
436}
437#[doc = "Possible values of the field `TCIE`"]
438#[derive(Clone, Copy, Debug, PartialEq)]
439pub enum TCIER {
440 #[doc = "Transfer Complete interrupt disabled"]
441 DISABLED,
442 #[doc = "Transfer Complete interrupt enabled"]
443 ENABLED,
444}
445impl TCIER {
446 #[doc = r" Returns `true` if the bit is clear (0)"]
447 #[inline]
448 pub fn bit_is_clear(&self) -> bool {
449 !self.bit()
450 }
451 #[doc = r" Returns `true` if the bit is set (1)"]
452 #[inline]
453 pub fn bit_is_set(&self) -> bool {
454 self.bit()
455 }
456 #[doc = r" Value of the field as raw bits"]
457 #[inline]
458 pub fn bit(&self) -> bool {
459 match *self {
460 TCIER::DISABLED => false,
461 TCIER::ENABLED => true,
462 }
463 }
464 #[allow(missing_docs)]
465 #[doc(hidden)]
466 #[inline]
467 pub fn _from(value: bool) -> TCIER {
468 match value {
469 false => TCIER::DISABLED,
470 true => TCIER::ENABLED,
471 }
472 }
473 #[doc = "Checks if the value of the field is `DISABLED`"]
474 #[inline]
475 pub fn is_disabled(&self) -> bool {
476 *self == TCIER::DISABLED
477 }
478 #[doc = "Checks if the value of the field is `ENABLED`"]
479 #[inline]
480 pub fn is_enabled(&self) -> bool {
481 *self == TCIER::ENABLED
482 }
483}
484#[doc = "Possible values of the field `EN`"]
485#[derive(Clone, Copy, Debug, PartialEq)]
486pub enum ENR {
487 #[doc = "Channel disabled"]
488 DISABLED,
489 #[doc = "Channel enabled"]
490 ENABLED,
491}
492impl ENR {
493 #[doc = r" Returns `true` if the bit is clear (0)"]
494 #[inline]
495 pub fn bit_is_clear(&self) -> bool {
496 !self.bit()
497 }
498 #[doc = r" Returns `true` if the bit is set (1)"]
499 #[inline]
500 pub fn bit_is_set(&self) -> bool {
501 self.bit()
502 }
503 #[doc = r" Value of the field as raw bits"]
504 #[inline]
505 pub fn bit(&self) -> bool {
506 match *self {
507 ENR::DISABLED => false,
508 ENR::ENABLED => true,
509 }
510 }
511 #[allow(missing_docs)]
512 #[doc(hidden)]
513 #[inline]
514 pub fn _from(value: bool) -> ENR {
515 match value {
516 false => ENR::DISABLED,
517 true => ENR::ENABLED,
518 }
519 }
520 #[doc = "Checks if the value of the field is `DISABLED`"]
521 #[inline]
522 pub fn is_disabled(&self) -> bool {
523 *self == ENR::DISABLED
524 }
525 #[doc = "Checks if the value of the field is `ENABLED`"]
526 #[inline]
527 pub fn is_enabled(&self) -> bool {
528 *self == ENR::ENABLED
529 }
530}
531#[doc = "Values that can be written to the field `MEM2MEM`"]
532pub enum MEM2MEMW {
533 #[doc = "Memory to memory mode disabled"]
534 DISABLED,
535 #[doc = "Memory to memory mode enabled"]
536 ENABLED,
537}
538impl MEM2MEMW {
539 #[allow(missing_docs)]
540 #[doc(hidden)]
541 #[inline]
542 pub fn _bits(&self) -> bool {
543 match *self {
544 MEM2MEMW::DISABLED => false,
545 MEM2MEMW::ENABLED => true,
546 }
547 }
548}
549#[doc = r" Proxy"]
550pub struct _MEM2MEMW<'a> {
551 w: &'a mut W,
552}
553impl<'a> _MEM2MEMW<'a> {
554 #[doc = r" Writes `variant` to the field"]
555 #[inline]
556 pub fn variant(self, variant: MEM2MEMW) -> &'a mut W {
557 {
558 self.bit(variant._bits())
559 }
560 }
561 #[doc = "Memory to memory mode disabled"]
562 #[inline]
563 pub fn disabled(self) -> &'a mut W {
564 self.variant(MEM2MEMW::DISABLED)
565 }
566 #[doc = "Memory to memory mode enabled"]
567 #[inline]
568 pub fn enabled(self) -> &'a mut W {
569 self.variant(MEM2MEMW::ENABLED)
570 }
571 #[doc = r" Sets the field bit"]
572 pub fn set_bit(self) -> &'a mut W {
573 self.bit(true)
574 }
575 #[doc = r" Clears the field bit"]
576 pub fn clear_bit(self) -> &'a mut W {
577 self.bit(false)
578 }
579 #[doc = r" Writes raw bits to the field"]
580 #[inline]
581 pub fn bit(self, value: bool) -> &'a mut W {
582 const MASK: bool = true;
583 const OFFSET: u8 = 14;
584 self.w.bits &= !((MASK as u32) << OFFSET);
585 self.w.bits |= ((value & MASK) as u32) << OFFSET;
586 self.w
587 }
588}
589#[doc = "Values that can be written to the field `PL`"]
590pub enum PLW {
591 #[doc = "Low priority"]
592 LOW,
593 #[doc = "Medium priority"]
594 MEDIUM,
595 #[doc = "High priority"]
596 HIGH,
597 #[doc = "Very high priority"]
598 VERYHIGH,
599}
600impl PLW {
601 #[allow(missing_docs)]
602 #[doc(hidden)]
603 #[inline]
604 pub fn _bits(&self) -> u8 {
605 match *self {
606 PLW::LOW => 0,
607 PLW::MEDIUM => 1,
608 PLW::HIGH => 2,
609 PLW::VERYHIGH => 3,
610 }
611 }
612}
613#[doc = r" Proxy"]
614pub struct _PLW<'a> {
615 w: &'a mut W,
616}
617impl<'a> _PLW<'a> {
618 #[doc = r" Writes `variant` to the field"]
619 #[inline]
620 pub fn variant(self, variant: PLW) -> &'a mut W {
621 {
622 self.bits(variant._bits())
623 }
624 }
625 #[doc = "Low priority"]
626 #[inline]
627 pub fn low(self) -> &'a mut W {
628 self.variant(PLW::LOW)
629 }
630 #[doc = "Medium priority"]
631 #[inline]
632 pub fn medium(self) -> &'a mut W {
633 self.variant(PLW::MEDIUM)
634 }
635 #[doc = "High priority"]
636 #[inline]
637 pub fn high(self) -> &'a mut W {
638 self.variant(PLW::HIGH)
639 }
640 #[doc = "Very high priority"]
641 #[inline]
642 pub fn very_high(self) -> &'a mut W {
643 self.variant(PLW::VERYHIGH)
644 }
645 #[doc = r" Writes raw bits to the field"]
646 #[inline]
647 pub fn bits(self, value: u8) -> &'a mut W {
648 const MASK: u8 = 3;
649 const OFFSET: u8 = 12;
650 self.w.bits &= !((MASK as u32) << OFFSET);
651 self.w.bits |= ((value & MASK) as u32) << OFFSET;
652 self.w
653 }
654}
655#[doc = "Values that can be written to the field `MSIZE`"]
656pub enum MSIZEW {
657 #[doc = "8-bit size"]
658 BIT8,
659 #[doc = "16-bit size"]
660 BIT16,
661 #[doc = "32-bit size"]
662 BIT32,
663}
664impl MSIZEW {
665 #[allow(missing_docs)]
666 #[doc(hidden)]
667 #[inline]
668 pub fn _bits(&self) -> u8 {
669 match *self {
670 MSIZEW::BIT8 => 0,
671 MSIZEW::BIT16 => 1,
672 MSIZEW::BIT32 => 2,
673 }
674 }
675}
676#[doc = r" Proxy"]
677pub struct _MSIZEW<'a> {
678 w: &'a mut W,
679}
680impl<'a> _MSIZEW<'a> {
681 #[doc = r" Writes `variant` to the field"]
682 #[inline]
683 pub fn variant(self, variant: MSIZEW) -> &'a mut W {
684 unsafe { self.bits(variant._bits()) }
685 }
686 #[doc = "8-bit size"]
687 #[inline]
688 pub fn bit8(self) -> &'a mut W {
689 self.variant(MSIZEW::BIT8)
690 }
691 #[doc = "16-bit size"]
692 #[inline]
693 pub fn bit16(self) -> &'a mut W {
694 self.variant(MSIZEW::BIT16)
695 }
696 #[doc = "32-bit size"]
697 #[inline]
698 pub fn bit32(self) -> &'a mut W {
699 self.variant(MSIZEW::BIT32)
700 }
701 #[doc = r" Writes raw bits to the field"]
702 #[inline]
703 pub unsafe fn bits(self, value: u8) -> &'a mut W {
704 const MASK: u8 = 3;
705 const OFFSET: u8 = 10;
706 self.w.bits &= !((MASK as u32) << OFFSET);
707 self.w.bits |= ((value & MASK) as u32) << OFFSET;
708 self.w
709 }
710}
711#[doc = "Values that can be written to the field `PSIZE`"]
712pub type PSIZEW = MSIZEW;
713#[doc = r" Proxy"]
714pub struct _PSIZEW<'a> {
715 w: &'a mut W,
716}
717impl<'a> _PSIZEW<'a> {
718 #[doc = r" Writes `variant` to the field"]
719 #[inline]
720 pub fn variant(self, variant: PSIZEW) -> &'a mut W {
721 unsafe { self.bits(variant._bits()) }
722 }
723 #[doc = "8-bit size"]
724 #[inline]
725 pub fn bit8(self) -> &'a mut W {
726 self.variant(MSIZEW::BIT8)
727 }
728 #[doc = "16-bit size"]
729 #[inline]
730 pub fn bit16(self) -> &'a mut W {
731 self.variant(MSIZEW::BIT16)
732 }
733 #[doc = "32-bit size"]
734 #[inline]
735 pub fn bit32(self) -> &'a mut W {
736 self.variant(MSIZEW::BIT32)
737 }
738 #[doc = r" Writes raw bits to the field"]
739 #[inline]
740 pub unsafe fn bits(self, value: u8) -> &'a mut W {
741 const MASK: u8 = 3;
742 const OFFSET: u8 = 8;
743 self.w.bits &= !((MASK as u32) << OFFSET);
744 self.w.bits |= ((value & MASK) as u32) << OFFSET;
745 self.w
746 }
747}
748#[doc = "Values that can be written to the field `MINC`"]
749pub enum MINCW {
750 #[doc = "Increment mode disabled"]
751 DISABLED,
752 #[doc = "Increment mode enabled"]
753 ENABLED,
754}
755impl MINCW {
756 #[allow(missing_docs)]
757 #[doc(hidden)]
758 #[inline]
759 pub fn _bits(&self) -> bool {
760 match *self {
761 MINCW::DISABLED => false,
762 MINCW::ENABLED => true,
763 }
764 }
765}
766#[doc = r" Proxy"]
767pub struct _MINCW<'a> {
768 w: &'a mut W,
769}
770impl<'a> _MINCW<'a> {
771 #[doc = r" Writes `variant` to the field"]
772 #[inline]
773 pub fn variant(self, variant: MINCW) -> &'a mut W {
774 {
775 self.bit(variant._bits())
776 }
777 }
778 #[doc = "Increment mode disabled"]
779 #[inline]
780 pub fn disabled(self) -> &'a mut W {
781 self.variant(MINCW::DISABLED)
782 }
783 #[doc = "Increment mode enabled"]
784 #[inline]
785 pub fn enabled(self) -> &'a mut W {
786 self.variant(MINCW::ENABLED)
787 }
788 #[doc = r" Sets the field bit"]
789 pub fn set_bit(self) -> &'a mut W {
790 self.bit(true)
791 }
792 #[doc = r" Clears the field bit"]
793 pub fn clear_bit(self) -> &'a mut W {
794 self.bit(false)
795 }
796 #[doc = r" Writes raw bits to the field"]
797 #[inline]
798 pub fn bit(self, value: bool) -> &'a mut W {
799 const MASK: bool = true;
800 const OFFSET: u8 = 7;
801 self.w.bits &= !((MASK as u32) << OFFSET);
802 self.w.bits |= ((value & MASK) as u32) << OFFSET;
803 self.w
804 }
805}
806#[doc = "Values that can be written to the field `PINC`"]
807pub type PINCW = MINCW;
808#[doc = r" Proxy"]
809pub struct _PINCW<'a> {
810 w: &'a mut W,
811}
812impl<'a> _PINCW<'a> {
813 #[doc = r" Writes `variant` to the field"]
814 #[inline]
815 pub fn variant(self, variant: PINCW) -> &'a mut W {
816 {
817 self.bit(variant._bits())
818 }
819 }
820 #[doc = "Increment mode disabled"]
821 #[inline]
822 pub fn disabled(self) -> &'a mut W {
823 self.variant(MINCW::DISABLED)
824 }
825 #[doc = "Increment mode enabled"]
826 #[inline]
827 pub fn enabled(self) -> &'a mut W {
828 self.variant(MINCW::ENABLED)
829 }
830 #[doc = r" Sets the field bit"]
831 pub fn set_bit(self) -> &'a mut W {
832 self.bit(true)
833 }
834 #[doc = r" Clears the field bit"]
835 pub fn clear_bit(self) -> &'a mut W {
836 self.bit(false)
837 }
838 #[doc = r" Writes raw bits to the field"]
839 #[inline]
840 pub fn bit(self, value: bool) -> &'a mut W {
841 const MASK: bool = true;
842 const OFFSET: u8 = 6;
843 self.w.bits &= !((MASK as u32) << OFFSET);
844 self.w.bits |= ((value & MASK) as u32) << OFFSET;
845 self.w
846 }
847}
848#[doc = "Values that can be written to the field `CIRC`"]
849pub enum CIRCW {
850 #[doc = "Circular buffer disabled"]
851 DISABLED,
852 #[doc = "Circular buffer enabled"]
853 ENABLED,
854}
855impl CIRCW {
856 #[allow(missing_docs)]
857 #[doc(hidden)]
858 #[inline]
859 pub fn _bits(&self) -> bool {
860 match *self {
861 CIRCW::DISABLED => false,
862 CIRCW::ENABLED => true,
863 }
864 }
865}
866#[doc = r" Proxy"]
867pub struct _CIRCW<'a> {
868 w: &'a mut W,
869}
870impl<'a> _CIRCW<'a> {
871 #[doc = r" Writes `variant` to the field"]
872 #[inline]
873 pub fn variant(self, variant: CIRCW) -> &'a mut W {
874 {
875 self.bit(variant._bits())
876 }
877 }
878 #[doc = "Circular buffer disabled"]
879 #[inline]
880 pub fn disabled(self) -> &'a mut W {
881 self.variant(CIRCW::DISABLED)
882 }
883 #[doc = "Circular buffer enabled"]
884 #[inline]
885 pub fn enabled(self) -> &'a mut W {
886 self.variant(CIRCW::ENABLED)
887 }
888 #[doc = r" Sets the field bit"]
889 pub fn set_bit(self) -> &'a mut W {
890 self.bit(true)
891 }
892 #[doc = r" Clears the field bit"]
893 pub fn clear_bit(self) -> &'a mut W {
894 self.bit(false)
895 }
896 #[doc = r" Writes raw bits to the field"]
897 #[inline]
898 pub fn bit(self, value: bool) -> &'a mut W {
899 const MASK: bool = true;
900 const OFFSET: u8 = 5;
901 self.w.bits &= !((MASK as u32) << OFFSET);
902 self.w.bits |= ((value & MASK) as u32) << OFFSET;
903 self.w
904 }
905}
906#[doc = "Values that can be written to the field `DIR`"]
907pub enum DIRW {
908 #[doc = "Read from peripheral"]
909 FROMPERIPHERAL,
910 #[doc = "Read from memory"]
911 FROMMEMORY,
912}
913impl DIRW {
914 #[allow(missing_docs)]
915 #[doc(hidden)]
916 #[inline]
917 pub fn _bits(&self) -> bool {
918 match *self {
919 DIRW::FROMPERIPHERAL => false,
920 DIRW::FROMMEMORY => true,
921 }
922 }
923}
924#[doc = r" Proxy"]
925pub struct _DIRW<'a> {
926 w: &'a mut W,
927}
928impl<'a> _DIRW<'a> {
929 #[doc = r" Writes `variant` to the field"]
930 #[inline]
931 pub fn variant(self, variant: DIRW) -> &'a mut W {
932 {
933 self.bit(variant._bits())
934 }
935 }
936 #[doc = "Read from peripheral"]
937 #[inline]
938 pub fn from_peripheral(self) -> &'a mut W {
939 self.variant(DIRW::FROMPERIPHERAL)
940 }
941 #[doc = "Read from memory"]
942 #[inline]
943 pub fn from_memory(self) -> &'a mut W {
944 self.variant(DIRW::FROMMEMORY)
945 }
946 #[doc = r" Sets the field bit"]
947 pub fn set_bit(self) -> &'a mut W {
948 self.bit(true)
949 }
950 #[doc = r" Clears the field bit"]
951 pub fn clear_bit(self) -> &'a mut W {
952 self.bit(false)
953 }
954 #[doc = r" Writes raw bits to the field"]
955 #[inline]
956 pub fn bit(self, value: bool) -> &'a mut W {
957 const MASK: bool = true;
958 const OFFSET: u8 = 4;
959 self.w.bits &= !((MASK as u32) << OFFSET);
960 self.w.bits |= ((value & MASK) as u32) << OFFSET;
961 self.w
962 }
963}
964#[doc = "Values that can be written to the field `TEIE`"]
965pub enum TEIEW {
966 #[doc = "Transfer Error interrupt disabled"]
967 DISABLED,
968 #[doc = "Transfer Error interrupt enabled"]
969 ENABLED,
970}
971impl TEIEW {
972 #[allow(missing_docs)]
973 #[doc(hidden)]
974 #[inline]
975 pub fn _bits(&self) -> bool {
976 match *self {
977 TEIEW::DISABLED => false,
978 TEIEW::ENABLED => true,
979 }
980 }
981}
982#[doc = r" Proxy"]
983pub struct _TEIEW<'a> {
984 w: &'a mut W,
985}
986impl<'a> _TEIEW<'a> {
987 #[doc = r" Writes `variant` to the field"]
988 #[inline]
989 pub fn variant(self, variant: TEIEW) -> &'a mut W {
990 {
991 self.bit(variant._bits())
992 }
993 }
994 #[doc = "Transfer Error interrupt disabled"]
995 #[inline]
996 pub fn disabled(self) -> &'a mut W {
997 self.variant(TEIEW::DISABLED)
998 }
999 #[doc = "Transfer Error interrupt enabled"]
1000 #[inline]
1001 pub fn enabled(self) -> &'a mut W {
1002 self.variant(TEIEW::ENABLED)
1003 }
1004 #[doc = r" Sets the field bit"]
1005 pub fn set_bit(self) -> &'a mut W {
1006 self.bit(true)
1007 }
1008 #[doc = r" Clears the field bit"]
1009 pub fn clear_bit(self) -> &'a mut W {
1010 self.bit(false)
1011 }
1012 #[doc = r" Writes raw bits to the field"]
1013 #[inline]
1014 pub fn bit(self, value: bool) -> &'a mut W {
1015 const MASK: bool = true;
1016 const OFFSET: u8 = 3;
1017 self.w.bits &= !((MASK as u32) << OFFSET);
1018 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1019 self.w
1020 }
1021}
1022#[doc = "Values that can be written to the field `HTIE`"]
1023pub enum HTIEW {
1024 #[doc = "Half Transfer interrupt disabled"]
1025 DISABLED,
1026 #[doc = "Half Transfer interrupt enabled"]
1027 ENABLED,
1028}
1029impl HTIEW {
1030 #[allow(missing_docs)]
1031 #[doc(hidden)]
1032 #[inline]
1033 pub fn _bits(&self) -> bool {
1034 match *self {
1035 HTIEW::DISABLED => false,
1036 HTIEW::ENABLED => true,
1037 }
1038 }
1039}
1040#[doc = r" Proxy"]
1041pub struct _HTIEW<'a> {
1042 w: &'a mut W,
1043}
1044impl<'a> _HTIEW<'a> {
1045 #[doc = r" Writes `variant` to the field"]
1046 #[inline]
1047 pub fn variant(self, variant: HTIEW) -> &'a mut W {
1048 {
1049 self.bit(variant._bits())
1050 }
1051 }
1052 #[doc = "Half Transfer interrupt disabled"]
1053 #[inline]
1054 pub fn disabled(self) -> &'a mut W {
1055 self.variant(HTIEW::DISABLED)
1056 }
1057 #[doc = "Half Transfer interrupt enabled"]
1058 #[inline]
1059 pub fn enabled(self) -> &'a mut W {
1060 self.variant(HTIEW::ENABLED)
1061 }
1062 #[doc = r" Sets the field bit"]
1063 pub fn set_bit(self) -> &'a mut W {
1064 self.bit(true)
1065 }
1066 #[doc = r" Clears the field bit"]
1067 pub fn clear_bit(self) -> &'a mut W {
1068 self.bit(false)
1069 }
1070 #[doc = r" Writes raw bits to the field"]
1071 #[inline]
1072 pub fn bit(self, value: bool) -> &'a mut W {
1073 const MASK: bool = true;
1074 const OFFSET: u8 = 2;
1075 self.w.bits &= !((MASK as u32) << OFFSET);
1076 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1077 self.w
1078 }
1079}
1080#[doc = "Values that can be written to the field `TCIE`"]
1081pub enum TCIEW {
1082 #[doc = "Transfer Complete interrupt disabled"]
1083 DISABLED,
1084 #[doc = "Transfer Complete interrupt enabled"]
1085 ENABLED,
1086}
1087impl TCIEW {
1088 #[allow(missing_docs)]
1089 #[doc(hidden)]
1090 #[inline]
1091 pub fn _bits(&self) -> bool {
1092 match *self {
1093 TCIEW::DISABLED => false,
1094 TCIEW::ENABLED => true,
1095 }
1096 }
1097}
1098#[doc = r" Proxy"]
1099pub struct _TCIEW<'a> {
1100 w: &'a mut W,
1101}
1102impl<'a> _TCIEW<'a> {
1103 #[doc = r" Writes `variant` to the field"]
1104 #[inline]
1105 pub fn variant(self, variant: TCIEW) -> &'a mut W {
1106 {
1107 self.bit(variant._bits())
1108 }
1109 }
1110 #[doc = "Transfer Complete interrupt disabled"]
1111 #[inline]
1112 pub fn disabled(self) -> &'a mut W {
1113 self.variant(TCIEW::DISABLED)
1114 }
1115 #[doc = "Transfer Complete interrupt enabled"]
1116 #[inline]
1117 pub fn enabled(self) -> &'a mut W {
1118 self.variant(TCIEW::ENABLED)
1119 }
1120 #[doc = r" Sets the field bit"]
1121 pub fn set_bit(self) -> &'a mut W {
1122 self.bit(true)
1123 }
1124 #[doc = r" Clears the field bit"]
1125 pub fn clear_bit(self) -> &'a mut W {
1126 self.bit(false)
1127 }
1128 #[doc = r" Writes raw bits to the field"]
1129 #[inline]
1130 pub fn bit(self, value: bool) -> &'a mut W {
1131 const MASK: bool = true;
1132 const OFFSET: u8 = 1;
1133 self.w.bits &= !((MASK as u32) << OFFSET);
1134 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1135 self.w
1136 }
1137}
1138#[doc = "Values that can be written to the field `EN`"]
1139pub enum ENW {
1140 #[doc = "Channel disabled"]
1141 DISABLED,
1142 #[doc = "Channel enabled"]
1143 ENABLED,
1144}
1145impl ENW {
1146 #[allow(missing_docs)]
1147 #[doc(hidden)]
1148 #[inline]
1149 pub fn _bits(&self) -> bool {
1150 match *self {
1151 ENW::DISABLED => false,
1152 ENW::ENABLED => true,
1153 }
1154 }
1155}
1156#[doc = r" Proxy"]
1157pub struct _ENW<'a> {
1158 w: &'a mut W,
1159}
1160impl<'a> _ENW<'a> {
1161 #[doc = r" Writes `variant` to the field"]
1162 #[inline]
1163 pub fn variant(self, variant: ENW) -> &'a mut W {
1164 {
1165 self.bit(variant._bits())
1166 }
1167 }
1168 #[doc = "Channel disabled"]
1169 #[inline]
1170 pub fn disabled(self) -> &'a mut W {
1171 self.variant(ENW::DISABLED)
1172 }
1173 #[doc = "Channel enabled"]
1174 #[inline]
1175 pub fn enabled(self) -> &'a mut W {
1176 self.variant(ENW::ENABLED)
1177 }
1178 #[doc = r" Sets the field bit"]
1179 pub fn set_bit(self) -> &'a mut W {
1180 self.bit(true)
1181 }
1182 #[doc = r" Clears the field bit"]
1183 pub fn clear_bit(self) -> &'a mut W {
1184 self.bit(false)
1185 }
1186 #[doc = r" Writes raw bits to the field"]
1187 #[inline]
1188 pub fn bit(self, value: bool) -> &'a mut W {
1189 const MASK: bool = true;
1190 const OFFSET: u8 = 0;
1191 self.w.bits &= !((MASK as u32) << OFFSET);
1192 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1193 self.w
1194 }
1195}
1196impl R {
1197 #[doc = r" Value of the register as raw bits"]
1198 #[inline]
1199 pub fn bits(&self) -> u32 {
1200 self.bits
1201 }
1202 #[doc = "Bit 14 - Memory to memory mode"]
1203 #[inline]
1204 pub fn mem2mem(&self) -> MEM2MEMR {
1205 MEM2MEMR::_from({
1206 const MASK: bool = true;
1207 const OFFSET: u8 = 14;
1208 ((self.bits >> OFFSET) & MASK as u32) != 0
1209 })
1210 }
1211 #[doc = "Bits 12:13 - Channel priority level"]
1212 #[inline]
1213 pub fn pl(&self) -> PLR {
1214 PLR::_from({
1215 const MASK: u8 = 3;
1216 const OFFSET: u8 = 12;
1217 ((self.bits >> OFFSET) & MASK as u32) as u8
1218 })
1219 }
1220 #[doc = "Bits 10:11 - Memory size"]
1221 #[inline]
1222 pub fn msize(&self) -> MSIZER {
1223 MSIZER::_from({
1224 const MASK: u8 = 3;
1225 const OFFSET: u8 = 10;
1226 ((self.bits >> OFFSET) & MASK as u32) as u8
1227 })
1228 }
1229 #[doc = "Bits 8:9 - Peripheral size"]
1230 #[inline]
1231 pub fn psize(&self) -> PSIZER {
1232 PSIZER::_from({
1233 const MASK: u8 = 3;
1234 const OFFSET: u8 = 8;
1235 ((self.bits >> OFFSET) & MASK as u32) as u8
1236 })
1237 }
1238 #[doc = "Bit 7 - Memory increment mode"]
1239 #[inline]
1240 pub fn minc(&self) -> MINCR {
1241 MINCR::_from({
1242 const MASK: bool = true;
1243 const OFFSET: u8 = 7;
1244 ((self.bits >> OFFSET) & MASK as u32) != 0
1245 })
1246 }
1247 #[doc = "Bit 6 - Peripheral increment mode"]
1248 #[inline]
1249 pub fn pinc(&self) -> PINCR {
1250 PINCR::_from({
1251 const MASK: bool = true;
1252 const OFFSET: u8 = 6;
1253 ((self.bits >> OFFSET) & MASK as u32) != 0
1254 })
1255 }
1256 #[doc = "Bit 5 - Circular mode"]
1257 #[inline]
1258 pub fn circ(&self) -> CIRCR {
1259 CIRCR::_from({
1260 const MASK: bool = true;
1261 const OFFSET: u8 = 5;
1262 ((self.bits >> OFFSET) & MASK as u32) != 0
1263 })
1264 }
1265 #[doc = "Bit 4 - Data transfer direction"]
1266 #[inline]
1267 pub fn dir(&self) -> DIRR {
1268 DIRR::_from({
1269 const MASK: bool = true;
1270 const OFFSET: u8 = 4;
1271 ((self.bits >> OFFSET) & MASK as u32) != 0
1272 })
1273 }
1274 #[doc = "Bit 3 - Transfer error interrupt enable"]
1275 #[inline]
1276 pub fn teie(&self) -> TEIER {
1277 TEIER::_from({
1278 const MASK: bool = true;
1279 const OFFSET: u8 = 3;
1280 ((self.bits >> OFFSET) & MASK as u32) != 0
1281 })
1282 }
1283 #[doc = "Bit 2 - Half transfer interrupt enable"]
1284 #[inline]
1285 pub fn htie(&self) -> HTIER {
1286 HTIER::_from({
1287 const MASK: bool = true;
1288 const OFFSET: u8 = 2;
1289 ((self.bits >> OFFSET) & MASK as u32) != 0
1290 })
1291 }
1292 #[doc = "Bit 1 - Transfer complete interrupt enable"]
1293 #[inline]
1294 pub fn tcie(&self) -> TCIER {
1295 TCIER::_from({
1296 const MASK: bool = true;
1297 const OFFSET: u8 = 1;
1298 ((self.bits >> OFFSET) & MASK as u32) != 0
1299 })
1300 }
1301 #[doc = "Bit 0 - Channel enable"]
1302 #[inline]
1303 pub fn en(&self) -> ENR {
1304 ENR::_from({
1305 const MASK: bool = true;
1306 const OFFSET: u8 = 0;
1307 ((self.bits >> OFFSET) & MASK as u32) != 0
1308 })
1309 }
1310}
1311impl W {
1312 #[doc = r" Reset value of the register"]
1313 #[inline]
1314 pub fn reset_value() -> W {
1315 W { bits: 0 }
1316 }
1317 #[doc = r" Writes raw bits to the register"]
1318 #[inline]
1319 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1320 self.bits = bits;
1321 self
1322 }
1323 #[doc = "Bit 14 - Memory to memory mode"]
1324 #[inline]
1325 pub fn mem2mem(&mut self) -> _MEM2MEMW {
1326 _MEM2MEMW { w: self }
1327 }
1328 #[doc = "Bits 12:13 - Channel priority level"]
1329 #[inline]
1330 pub fn pl(&mut self) -> _PLW {
1331 _PLW { w: self }
1332 }
1333 #[doc = "Bits 10:11 - Memory size"]
1334 #[inline]
1335 pub fn msize(&mut self) -> _MSIZEW {
1336 _MSIZEW { w: self }
1337 }
1338 #[doc = "Bits 8:9 - Peripheral size"]
1339 #[inline]
1340 pub fn psize(&mut self) -> _PSIZEW {
1341 _PSIZEW { w: self }
1342 }
1343 #[doc = "Bit 7 - Memory increment mode"]
1344 #[inline]
1345 pub fn minc(&mut self) -> _MINCW {
1346 _MINCW { w: self }
1347 }
1348 #[doc = "Bit 6 - Peripheral increment mode"]
1349 #[inline]
1350 pub fn pinc(&mut self) -> _PINCW {
1351 _PINCW { w: self }
1352 }
1353 #[doc = "Bit 5 - Circular mode"]
1354 #[inline]
1355 pub fn circ(&mut self) -> _CIRCW {
1356 _CIRCW { w: self }
1357 }
1358 #[doc = "Bit 4 - Data transfer direction"]
1359 #[inline]
1360 pub fn dir(&mut self) -> _DIRW {
1361 _DIRW { w: self }
1362 }
1363 #[doc = "Bit 3 - Transfer error interrupt enable"]
1364 #[inline]
1365 pub fn teie(&mut self) -> _TEIEW {
1366 _TEIEW { w: self }
1367 }
1368 #[doc = "Bit 2 - Half transfer interrupt enable"]
1369 #[inline]
1370 pub fn htie(&mut self) -> _HTIEW {
1371 _HTIEW { w: self }
1372 }
1373 #[doc = "Bit 1 - Transfer complete interrupt enable"]
1374 #[inline]
1375 pub fn tcie(&mut self) -> _TCIEW {
1376 _TCIEW { w: self }
1377 }
1378 #[doc = "Bit 0 - Channel enable"]
1379 #[inline]
1380 pub fn en(&mut self) -> _ENW {
1381 _ENW { w: self }
1382 }
1383}